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Commits on Jul 22, 2021

• Fix riscv-software-src#352 (riscv-software-src#353)

  daniellustig

  committedJul 22, 2021
  e30978a

Commits on Jul 21, 2021

• Move the Svnapot test to its own folder (riscv-software-src#351)

  daniellustig

  committedJul 21, 2021
  ba13606

Commits on Jul 20, 2021

• Bump env

  aswaterman

  committedJul 20, 2021
  133856d

Commits on Jul 19, 2021

• Add a test for Svnapot (riscv-software-src#349)

  daniellustig

  committedJul 19, 2021
  fb2d8ec

• Debug tests: catch write to nonexistent trigger registers in entry.S (riscv-software-src#348)

  Wren6991

  committedJul 19, 2021
  eeacd55

Commits on Jun 29, 2021

• Update README.md (riscv-software-src#342)

  mymatin

  committedJun 29, 2021
  5ce1c35

Commits on Jun 8, 2021

• Tweaks for multispike. (riscv-software-src#339)

  timsifive

  committedJun 8, 2021
  30e15bf

Commits on Jun 2, 2021

• Enable access to cycle counter before trying to write it

  aswaterman

  committedJun 2, 2021
  1b2c3ea

• Test all four ways of reading a read-only CSR

  aswaterman

  committedJun 2, 2021
  3e175a0

Commits on May 20, 2021

• Test multiple heterogeneous spike instances. (riscv-software-src#338)

  timsifive

  committedMay 20, 2021
  09cfdaa

Commits on May 12, 2021

• Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: (riscv-software-src#337)

  

  slametr-sifive

  and

  Slamet Rianto

  committedMay 12, 2021
  069ccc6

Commits on May 10, 2021

• Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support CLIC mode. (riscv-software-src#336)

  

  slametr-sifive

  and

  Slamet Rianto

  committedMay 10, 2021
  c22b105

Commits on May 7, 2021

• Test daisy chained homogeneous spike instances. (riscv-software-src#334)

  timsifive

  committedMay 7, 2021
  c9f43c1

Commits on Apr 13, 2021

• Add FreeRTOS smoke tests. (riscv-software-src#333)

  timsifive

  committedApr 13, 2021
  1b05661

Commits on Feb 11, 2021

• Add early_applicable() to a few tests. (riscv-software-src#325)

  timsifive

  committedFeb 11, 2021
  1ce128f

Commits on Feb 2, 2021

• Align mtvec in rv32mi-p-shamt test

  aswaterman

  committedFeb 2, 2021
  8b90534

• Prevent GCC from pattern-matching the memset implementation

  aswaterman

  committedFeb 2, 2021
  ea85805

Commits on Jan 25, 2021

• Smoketest that vl and vtype can be modified. (riscv-software-src#320)

  timsifive

  committedJan 25, 2021
  e759318

Commits on Jan 9, 2021

• Don't rely on the implementation-specific WFI time limit (riscv-software-src#318)

  pdonahue-ventana

  committedJan 9, 2021
  e35ee28

Commits on Jan 8, 2021

• Disable V extension when compiler doesn't support it. (riscv-software-src#317)

  timsifive

  committedJan 8, 2021
  4743239

• Park other harts in TranslateTest. (riscv-software-src#313)

  timsifive

  committedJan 8, 2021
  cd6ebbc

Commits on Jan 7, 2021

• Stop testing -rtos riscv. (riscv-software-src#314)

  timsifive

  committedJan 7, 2021
  363e5cf

Commits on Jan 4, 2021

• Disable rv32ua/rv64ua LR/SC test case 4 (riscv-software-src#316)

  ben-marshall

  committedJan 4, 2021
  94be324

Commits on Dec 31, 2020

• Make HiFiveUnleashed tests clean.

  timsifive

  committedDec 31, 2020
  7d06966

Commits on Dec 18, 2020

• Add test for new OpenOCD riscv info command. (riscv-software-src#310)

  timsifive

  committedDec 18, 2020
  3496243

• Revive and expand invalid read test. (riscv-software-src#309)

  timsifive

  committedDec 18, 2020
  f7e9ef1

Commits on Dec 16, 2020

• Refactor rv64ud structural test to match format of other tests (riscv-software-src#311)

  

  Kathlene Hurt

  committedDec 16, 2020
  b0b3d24

Commits on Dec 14, 2020

• Add tests for memory sampling feature. (riscv-software-src#300)

  timsifive

  committedDec 14, 2020
  67cb468

Commits on Dec 8, 2020

• Add rd=x0 test case to csr test (riscv-software-src#308)

  takahirox

  committedDec 8, 2020
  cbeadfd

• Fix minor typo (riscv-software-src#307)

  takahirox

  committedDec 8, 2020
  4a54e2b

Commits on Nov 21, 2020

• Only attempt to build tests supported by compiler

  aswaterman

  committedNov 21, 2020
  58eb560

Commits on Nov 11, 2020

• add zfh (float16) test case and related macros (riscv-software-src#301)

  chihminchao

  committedNov 11, 2020
  5f8a491

Commits on Oct 19, 2020

• use registers present on rv32e (riscv-software-src#299)

  SandeepRajendran

  committedOct 19, 2020
  c4217d8

Commits on Oct 15, 2020

• bump env (riscv-software-src#298)

  SandeepRajendran

  committedOct 15, 2020
  44b343d

Commits on Oct 8, 2020

• Expose registers on all harts in openocd cfgs (riscv-software-src#297)

  sobuch

  committedOct 8, 2020
  ce7ec3b

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