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Commits on Oct 2, 2020

• Modify PMP benchmark to detect granularity (riscv-software-src#295)

  Moschn

  committedOct 2, 2020
  f1d5f44

Commits on Aug 31, 2020

• Add test for riscv repeat_read. (riscv-software-src#293)

  timsifive

  committedAug 31, 2020
  a5d8386

Commits on Aug 12, 2020

• Point people at a compiler that supports vectors. (riscv-software-src#290)

  timsifive

  committedAug 12, 2020
  14f08f8

Commits on Aug 6, 2020

• Add enable_rtos_riscv (riscv-software-src#288)

  timsifive

  committedAug 6, 2020
  f68760e

Commits on Jul 14, 2020

• bump env to fix riscv-software-src#286

  aswaterman

  committedJul 14, 2020
  3261a31

Commits on Jul 1, 2020

• Make pylint happy. (riscv-software-src#285)

  timsifive

  committedJul 1, 2020
  f92842f

Commits on Jun 25, 2020

• Add manual hwbp test. (riscv-software-src#283)

  timsifive

  committedJun 25, 2020
  08674a7

• Create a more sophisticated vector test (riscv-software-src#284)

  timsifive

  committedJun 25, 2020
  944704e

Commits on May 26, 2020

• Test semihosting calls (riscv-software-src#280)

  timsifive

  committedMay 26, 2020
  fbe74f4

Commits on May 18, 2020

• Parse "cannot insert breakpoint" message. (riscv-software-src#279)

  timsifive

  committedMay 18, 2020
  bc4c1d2

Commits on May 13, 2020

• Update env (riscv-software-src#275)

  pdonahue-ventana

  committedMay 13, 2020
  92c9171

Commits on Apr 17, 2020

• The HTIF device must live in its own page since it is (generally) a bus/hardware device (riscv-software-src#274)

  aharris-ventana

  committedApr 17, 2020
  3d3f29e

Commits on Apr 10, 2020

• Make TooManyHwbp more thorough. (riscv-software-src#272)

  timsifive

  committedApr 10, 2020
  2a869e0

• Change slen to a value that spike supports. (riscv-software-src#271)

  timsifive

  committedApr 10, 2020
  f2107b6

Commits on Mar 30, 2020

• Add debug-check-fast target for

  aswaterman

  committedMar 30, 2020
  19bfdab

Commits on Mar 26, 2020

• Improve address translation tests (riscv-software-src#261)

  timsifive

  committedMar 26, 2020
  7351b31

• Write a NOP program in PrivRw test. (riscv-software-src#260)

  timsifive

  committedMar 26, 2020
  094985d

Commits on Mar 21, 2020

• Fix regression introduced by 24d7d6b

  aswaterman

  committedMar 21, 2020
  5fe6092

• Move self-modifying 'fence.i' ops to .data memory section (riscv-software-src#269)

  

  WRansohoff

  and

  WRR

  committedMar 21, 2020
  8333b4f

Commits on Mar 19, 2020

• Fix comments error in fmin.S (riscv-software-src#267)

  mohanson

  committedMar 19, 2020
  08cbae4

Commits on Mar 18, 2020

• Spike changed --varch syntax (riscv-software-src#257)

  timsifive

  committedMar 18, 2020
  6c53e59

• Specify misa for HiFive Unleashed. (riscv-software-src#259)

  timsifive

  committedMar 18, 2020
  b436c73

• Have both rs=rd and rs!=rd cases in csr.S (riscv-software-src#263)

  takahirox

  committedMar 18, 2020
  24d7d6b

• Fix shamt.S header (riscv-software-src#264)

  takahirox

  committedMar 18, 2020
  f04e824

Commits on Mar 16, 2020

• Add a test case rs = rd to jalr.S (riscv-software-src#258)

  takahirox

  committedMar 16, 2020
  b59b7b8

Commits on Mar 11, 2020

• Add comment explaining convoluted rv64mi-p-scall behavior

  aswaterman

  committedMar 11, 2020
  272093f

• Revert "scall: make the intention of the test in machine mode more clear (riscv-software-src#246)"

  aswaterman

  committedMar 11, 2020
  ee576c0

• Setup a multilevel page table to avoid misaligned superpages caused by variable DRAM_BASE (riscv-software-src#255)

  cedric-orban

  committedMar 11, 2020
  72d284b

Commits on Mar 7, 2020

• Don't assume reset state of mscratch (riscv-software-src#254)

  pdonahue-ventana

  committedMar 7, 2020
  60e314e

Commits on Mar 6, 2020

• bump env (riscv-software-src#253)

  HanKuanChen

  committedMar 6, 2020
  0ab4c3c

• Bump riscv-test-env (riscv-software-src#252)

  aswaterman

  committedMar 6, 2020
  b751373

Commits on Mar 5, 2020

• Clean up gdb parsing code. (riscv-software-src#247)

  timsifive

  committedMar 5, 2020
  3109b4d

• Add a simple mechanism to skip tests on targets. (riscv-software-src#251)

  timsifive

  committedMar 5, 2020
  34b02fd

Commits on Mar 3, 2020

• enable rv32e compatability by replacing reg x29 with reg x7 (riscv-software-src#250)

  cedric-orban

  committedMar 3, 2020
  fb0510f

Commits on Feb 28, 2020

• bump env

  aswaterman

  committedFeb 28, 2020
  a46bbcf

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