A FPGA friendly 32 bit RISC-V CPU implementation

NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching

SonicBOOM: The Berkeley Out-of-Order Machine

Master programming by recreating your favorite technologies from scratch.

计算机自学指南

《Hello 算法》：动画图解、一键运行的数据结构与算法教程。支持 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 代码。简体版和繁体版同步更新，English version ongoing

A sim for prefetcher

Repository to host and maintain scale-sim-v2 code

buildroot fork

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Linux kernel source tree

RISC-V Linux Port

Xv6 for RISC-V

RISC-V SoC designed by students in UCAS

TensorFlow code and pre-trained models for BERT

Machine learning compiler based on MLIR for Sophgo TPU.

在SiFive Inclusive Cache上实现预取

Collect some CS textbooks for learning.

Mill is a fast JVM build tool that supports Java and Scala. 2-3x faster than Gradle and 5-10x faster than Maven for common workflows, Mill aims to make your project’s build process performant, main…

📚 计算机体系结构与C++书籍收集(持续更新)

Open-source high-performance RISC-V processor

A Library of Chisel3 Tools for Digital Signal Processing

Chisel: A Modern Hardware Design Language

Simple RISC-V 3-stage Pipeline in Chisel

MICRO22 artifact evaluation for Sparseloop

A conda-forge distribution.