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out-of-order55/README.md

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⚡ 我的技术栈 | My Tech Stack

  • systemverilog verilog c python

  • verilator quartus vivado

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  1. booth-multiplier booth-multiplier Public

    基4booth乘法器设计与验证

    VHDL 7

  2. DCache DCache Public

    2 way|PLRU|2*4k

    SystemVerilog 4

  3. ysyxsoc ysyxsoc Public

    一生一芯soc项目备份

    Verilog 3

  4. SRT-Divider SRT-Divider Public

    简单的未优化的SRT除法器

    Verilog 4

  5. cache-sim cache-sim Public

    一个可配置的cachesim

    C 1

  6. ysyx-question ysyx-question Public

    一生一芯必答题

    1