[AMDGPU] Use a generic printer for NamedIntOperands. #100399
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@llvm/pr-subscribers-backend-amdgpu Author: Ivan Kosarev (kosarev) ChangesFull diff: https://github.com/llvm/llvm-project/pull/100399.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 37bb9675d8c1d..b480b79ca764b 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -76,11 +76,6 @@ void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
}
-void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
-}
-
void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
@@ -135,24 +130,6 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
}
}
-void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- if (MI->getOperand(OpNo).getImm()) {
- O << " offset0:";
- printU8ImmDecOperand(MI, OpNo, O);
- }
-}
-
-void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- if (MI->getOperand(OpNo).getImm()) {
- O << " offset1:";
- printU8ImmDecOperand(MI, OpNo, O);
- }
-}
-
void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -165,13 +142,6 @@ void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
O << formatHex(MI->getOperand(OpNo).getImm());
}
-void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " offset:";
- printSMEMOffset(MI, OpNo, STI, O);
-}
-
void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -698,26 +668,6 @@ void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
O << " blgp:" << Imm;
}
-void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- unsigned Imm = MI->getOperand(OpNo).getImm();
- if (!Imm)
- return;
-
- O << " cbsz:" << Imm;
-}
-
-void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- unsigned Imm = MI->getOperand(OpNo).getImm();
- if (!Imm)
- return;
-
- O << " abid:" << Imm;
-}
-
void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -731,34 +681,6 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
O << ", ";
}
-void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_vdst:";
- printU4ImmDecOperand(MI, OpNo, O);
-}
-
-void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_va_vdst:";
- printU4ImmDecOperand(MI, OpNo, O);
-}
-
-void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_vm_vsrc:";
- printU4ImmDecOperand(MI, OpNo, O);
-}
-
-void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " wait_exp:";
- printU4ImmDecOperand(MI, OpNo, O);
-}
-
bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
unsigned OpNo) const {
return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
@@ -1155,29 +1077,6 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
}
}
-void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " row_mask:";
- printU4ImmOperand(MI, OpNo, STI, O);
-}
-
-void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- O << " bank_mask:";
- printU4ImmOperand(MI, OpNo, STI, O);
-}
-
-void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- unsigned Imm = MI->getOperand(OpNo).getImm();
- if (Imm) {
- O << " bound_ctrl:1";
- }
-}
-
void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
using namespace llvm::AMDGPU::DPP;
@@ -1812,14 +1711,18 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
O << ' ' << formatDec(Imm);
}
-void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- uint8_t Imm = MI->getOperand(OpNo).getImm();
- if (!Imm)
- return;
-
- O << " byte_sel:" << formatDec(Imm);
+void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O, StringRef Prefix,
+ unsigned Width, bool PrintInHex,
+ bool AlwaysPrint) {
+ int64_t V = MI->getOperand(OpNo).getImm();
+ if (AlwaysPrint || V != 0) {
+ if (Width)
+ V &= maxUIntN(Width);
+
+ O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
+ }
}
#include "AMDGPUGenAsmWriter.inc"
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
index d6d7fd34b68cc..fba8bc5cb6aa6 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
@@ -41,7 +41,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
@@ -52,16 +51,10 @@ class AMDGPUInstPrinter : public MCInstPrinter {
void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printSMEMOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
- void printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printCPol(const MCInst *MI, unsigned OpNo,
@@ -114,12 +107,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printDppRowMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
- void printDppBankMask(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
- void printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printDppFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
@@ -158,21 +145,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printWaitEXP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
- void printWaitVAVDst(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
- void printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O, unsigned N);
@@ -186,8 +161,10 @@ class AMDGPUInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printExpTgt(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
- void printByteSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
+ void printNamedInt(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O,
+ StringRef Prefix, unsigned Width, bool PrintInHex,
+ bool AlwaysPrint);
public:
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 873e42aa0fed3..9dbdd290149f0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1015,18 +1015,30 @@ def SDWAVopcDst : BoolRC {
let PrintMethod = "printVOPDst";
}
-class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
+class NamedIntOperand<ValueType Type, string prefix, bit Optional = 1,
string name = NAME>
: CustomOperand<Type, Optional, name> {
+ string Prefix = prefix;
+
let PredicateMethod =
"getPredicate([](const AMDGPUOperand &Op) -> bool { "#
"return Op.isImmTy(AMDGPUOperand::"#ImmTy#"); })";
+
string Validator = "[](int64_t V) { return true; }";
string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
let ParserMethod =
"[this](OperandVector &Operands) -> ParseStatus { "#
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
"AMDGPUOperand::"#ImmTy#", "#ConvertMethod#"); }";
+
+ bit PrintInHex = 0;
+ bit AlwaysPrint = 0;
+ int Width = 0;
+ let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "
+ "const MCSubtargetInfo &STI, raw_ostream &O) { "
+ "printNamedInt(MI, OpNo, STI, O, \""#Prefix#"\", "#
+ Width#", "#!if(PrintInHex, "true", "false")#", "#
+ !if(AlwaysPrint, "true", "false")#"); }";
}
class NamedBitOperand<string Id, string Name = NAME>
@@ -1065,6 +1077,7 @@ class ArrayOperand0<string Id, string Name = NAME>
let ImmTy = "ImmTyOffset" in
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
+let PrintMethod = "printOffset" in
def Offset : NamedIntOperand<i32, "offset">;
let Validator = "isUInt<8>" in {
def Offset0 : NamedIntOperand<i8, "offset0">;
@@ -1103,6 +1116,7 @@ def exp_vm : NamedBitOperand<"vm", "ExpVM">;
def FORMAT : CustomOperand<i8>;
+let PrintMethod = "printDMask" in
def DMask : NamedIntOperand<i16, "dmask">;
def Dim : CustomOperand<i8, /*optional=*/1>;
@@ -1123,7 +1137,7 @@ def IndexKey8bit : CustomOperand<i32, 1>;
def dpp8 : CustomOperand<i32, 0, "DPP8">;
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
-let DefaultValue = "0xf" in {
+let DefaultValue = "0xf", PrintInHex = 1, AlwaysPrint = 1, Width = 4 in {
def DppRowMask : NamedIntOperand<i32, "row_mask">;
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
}
@@ -1131,8 +1145,9 @@ def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
}
-let DecoderMethod = "decodeDpp8FI" in
+let DecoderMethod = "decodeDpp8FI", PrintMethod = "printDppFI" in
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
+let PrintMethod = "printDppFI" in
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
def blgp : CustomOperand<i32, 1, "BLGP">;
@@ -1146,6 +1161,7 @@ def hwreg : CustomOperand<i32, 0, "Hwreg">;
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
+let AlwaysPrint = 1 in {
def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
let Validator = "isUInt<4>";
}
@@ -1158,6 +1174,7 @@ def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
let Validator = "isUInt<1>";
}
+} // End AlwaysPrint = 1
def ByteSel : NamedIntOperand<i8, "byte_sel"> {
let Validator = "isUInt<2>";
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 9e470e27272c3..04a53174ed32f 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -11,7 +11,10 @@ def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
let EncoderMethod = "getSMEMOffsetEncoding",
DecoderMethod = "decodeSMEMOffset" in {
def SMEMOffset : ImmOperand<i32, "SMEMOffset", 1>;
-def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0>;
+def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0> {
+ let AlwaysPrint = 1;
+ let PrintInHex = 1;
+}
def OptSMEMOffsetMod : NamedIntOperand<i32, "offset"> {
let ImmTy = SMEMOffsetMod.ImmTy;
let PredicateMethod = SMEMOffsetMod.PredicateMethod;
|
jayfoad
reviewed
Jul 24, 2024
| int64_t V = MI->getOperand(OpNo).getImm(); | ||
| if (AlwaysPrint || V != 0) { | ||
| if (Width) | ||
| V &= maxUIntN(Width); |
There was a problem hiding this comment.
This should go before the V != 0 check, otherwise you can end up printing 0 when AlwaysPrint is false.
There was a problem hiding this comment.
I think if we drop significant bits here, then this should rather suggest the operand has a value that it's not supposed to have. This made me wondering why do we need the masking in the first place, which turns out we don't.
This includes simplifying printing dmask modifiers where we don't need to mask the value to print. Part of <llvm#62629>.
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This includes simplifying printing dmask modifiers where we don't need to mask the value to print. Part of <llvm#62629>.
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This includes simplifying printing dmask modifiers where we don't need to mask the value to print.
Part of #62629.