diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index c31f85dbea127f..a75391fcfa8a4e 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -119,20 +119,6 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (int64_t Offset = MI->getOperand(OpNo).getImm()) - O << " offset0:" << formatDec(Offset); -} - -void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - if (int64_t Offset = MI->getOperand(OpNo).getImm()) - O << " offset1:" << formatDec(Offset); -} - void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -145,13 +131,6 @@ void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo, O << formatHex(MI->getOperand(OpNo).getImm()); } -void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " offset:"; - printSMEMOffset(MI, OpNo, STI, O); -} - void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -269,14 +248,6 @@ void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) { return; } -void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O) { - if (MI->getOperand(OpNo).getImm()) { - O << " dmask:"; - printU16ImmOperand(MI, OpNo, STI, O); - } -} - void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Dim = MI->getOperand(OpNo).getImm(); @@ -678,26 +649,6 @@ void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo, O << " blgp:" << Imm; } -void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNo).getImm(); - if (!Imm) - return; - - O << " cbsz:" << Imm; -} - -void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNo).getImm(); - if (!Imm) - return; - - O << " abid:" << Imm; -} - void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -711,30 +662,6 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand, O << ", "; } -void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " wait_vdst:" << formatDec(MI->getOperand(OpNo).getImm()); -} - -void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " wait_va_vdst:" << formatDec(MI->getOperand(OpNo).getImm()); -} - -void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " wait_vm_vsrc:" << formatDec(MI->getOperand(OpNo).getImm()); -} - -void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " wait_exp:" << formatDec(MI->getOperand(OpNo).getImm()); -} - bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const { return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) && @@ -1127,18 +1054,6 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, } } -void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " row_mask:" << formatHex(MI->getOperand(OpNo).getImm()); -} - -void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - O << " bank_mask:" << formatHex(MI->getOperand(OpNo).getImm()); -} - void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -1782,14 +1697,13 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo, O << ' ' << formatDec(Imm); } -void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint8_t Imm = MI->getOperand(OpNo).getImm(); - if (!Imm) - return; - - O << " byte_sel:" << formatDec(Imm); +void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O, StringRef Prefix, + bool PrintInHex, bool AlwaysPrint) { + int64_t V = MI->getOperand(OpNo).getImm(); + if (AlwaysPrint || V != 0) + O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V)); } #include "AMDGPUGenAsmWriter.inc" diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h index 4a39022aea7cfd..4d44db5d9d818c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -48,24 +48,16 @@ class AMDGPUInstPrinter : public MCInstPrinter { void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); void printSMRDOffset8(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printSMEMOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printSMEMOffsetMod(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printCPol(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printTH(const MCInst *MI, int64_t TH, int64_t Scope, raw_ostream &O); void printScope(int64_t Scope, raw_ostream &O); - void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); void printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, @@ -110,10 +102,6 @@ class AMDGPUInstPrinter : public MCInstPrinter { raw_ostream &O); void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printDppRowMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printDppBankMask(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); void printDppBoundCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printDppFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, @@ -154,21 +142,9 @@ class AMDGPUInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const; void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI, raw_ostream &O); - void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printWaitEXP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); - void printWaitVAVDst(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); - void printWaitVMVSrc(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, unsigned N); @@ -182,8 +158,9 @@ class AMDGPUInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); void printExpTgt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printByteSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, - raw_ostream &O); + void printNamedInt(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O, + StringRef Prefix, bool PrintInHex, bool AlwaysPrint); public: static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 00a8b159c95262..e8a67ab6f7e94c 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1015,18 +1015,29 @@ def SDWAVopcDst : BoolRC { let PrintMethod = "printVOPDst"; } -class NamedIntOperand : CustomOperand { + string Prefix = prefix; + let PredicateMethod = "getPredicate([](const AMDGPUOperand &Op) -> bool { "# "return Op.isImmTy(AMDGPUOperand::"#ImmTy#"); })"; + string Validator = "[](int64_t V) { return true; }"; string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }"; let ParserMethod = "[this](OperandVector &Operands) -> ParseStatus { "# "return parseIntWithPrefix(\""#Prefix#"\", Operands, "# "AMDGPUOperand::"#ImmTy#", "#ConvertMethod#"); }"; + + bit PrintInHex = 0; + bit AlwaysPrint = 0; + let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, " + "const MCSubtargetInfo &STI, raw_ostream &O) { " + "printNamedInt(MI, OpNo, STI, O, \""#Prefix#"\", "# + !if(PrintInHex, "true", "false")#", "# + !if(AlwaysPrint, "true", "false")#"); }"; } class NamedBitOperand @@ -1065,6 +1076,7 @@ class ArrayOperand0 let ImmTy = "ImmTyOffset" in def flat_offset : CustomOperand; +let PrintMethod = "printOffset" in def Offset : NamedIntOperand; let Validator = "isUInt<8>" in { def Offset0 : NamedIntOperand; @@ -1103,6 +1115,7 @@ def exp_vm : NamedBitOperand<"vm", "ExpVM">; def FORMAT : CustomOperand; +let PrintInHex = 1 in def DMask : NamedIntOperand; def Dim : CustomOperand; @@ -1123,16 +1136,18 @@ def IndexKey8bit : CustomOperand; def dpp8 : CustomOperand; def dpp_ctrl : CustomOperand; -let DefaultValue = "0xf" in { +let DefaultValue = "0xf", PrintInHex = 1, AlwaysPrint = 1 in { def DppRowMask : NamedIntOperand; def DppBankMask : NamedIntOperand; } def DppBoundCtrl : NamedIntOperand { let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }"; + let PrintMethod = "printDppBoundCtrl"; } -let DecoderMethod = "decodeDpp8FI" in +let DecoderMethod = "decodeDpp8FI", PrintMethod = "printDppFI" in def Dpp8FI : NamedIntOperand; +let PrintMethod = "printDppFI" in def Dpp16FI : NamedIntOperand; def blgp : CustomOperand; @@ -1146,6 +1161,7 @@ def hwreg : CustomOperand; def exp_tgt : CustomOperand; +let AlwaysPrint = 1 in { def WaitVDST : NamedIntOperand { let Validator = "isUInt<4>"; } @@ -1158,6 +1174,7 @@ def WaitVAVDst : NamedIntOperand { def WaitVMVSrc : NamedIntOperand { let Validator = "isUInt<1>"; } +} // End AlwaysPrint = 1 def ByteSel : NamedIntOperand { let Validator = "isUInt<2>"; diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index 4218b7d4cbd5d5..625181f246557e 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -11,7 +11,10 @@ def smrd_offset_8 : ImmOperand; let EncoderMethod = "getSMEMOffsetEncoding", DecoderMethod = "decodeSMEMOffset" in { def SMEMOffset : ImmOperand; -def SMEMOffsetMod : NamedIntOperand; +def SMEMOffsetMod : NamedIntOperand { + let AlwaysPrint = 1; + let PrintInHex = 1; +} def OptSMEMOffsetMod : NamedIntOperand { let ImmTy = SMEMOffsetMod.ImmTy; let PredicateMethod = SMEMOffsetMod.PredicateMethod;