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Basic Risc V core implemented in Verilog and simulated in Vivado. The processor will execute the risc v 32 bit instruction set.

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Name		Name	Last commit message	Last commit date
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RISCV_sim (images)		RISCV_sim (images)
sim_1/new		sim_1/new
sources_1/new		sources_1/new
README.md		README.md

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Fyre-core-RV32I

Basic Risc V core implemented in Verilog and simulated in Vivado. The processor will execute the risc v 32 bit instruction set.

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Basic Risc V core implemented in Verilog and simulated in Vivado. The processor will execute the risc v 32 bit instruction set.

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