I am a student at San Diego State. I am working towards a Bachelors degree for Computer Engineering. I enjoy working on embedded systems and Verilog projects.
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Fyre-core-RV32I
Fyre-core-RV32I PublicBasic Risc V core implemented in Verilog and simulated in Vivado. The processor will execute the risc v 32 bit instruction set.
Verilog 1
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