Skip to content
View Traviste's full-sized avatar

Block or report Traviste

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. pa3_TaskSchedule pa3_TaskSchedule Public

    Python 2

  2. Fyre-core-RV32I Fyre-core-RV32I Public

    Basic Risc V core implemented in Verilog and simulated in Vivado. The processor will execute the risc v 32 bit instruction set.

    Verilog 1

  3. Encoded_Lock-machine Encoded_Lock-machine Public

    Verilog

  4. KoolServer KoolServer Public

    C