Releases: DigitalLogicSimCommunity/Digital-Logic-Sim-CE
Releases · DigitalLogicSimCommunity/Digital-Logic-Sim-CE
v0.39.1
v0.39.1
This version includes #41 issue fix by @VitoBarra.
Thank you Vito for the quick fix, and thank you @crispeeweevile for the equally fast report.
v0.39.0
We are glad to announce a new version with numerous fixes, expanded features, customizable clock and more.
Huge thanks to @VitoBarra for even making this new version possible and to all contributors.
Everyone is invited to open any Issues, Discussions and PRs to help improve the program.
New features
- New clock chip with customizable Hz (by @VitoBarra)
- Added new feature regarding folders:
- Renaming folders (by @VitoBarra)
- Deleting folders (by @VitoBarra)
- Moving chips between folders (by @VitoBarra)
- Fallback folder to handle compatibility issues (by @VitoBarra)
- Set target FPS or enable vSync from settings (by @AOx0)
Changes
- Reworked the focus system used to handle interaction, now adding a new key-binding option should be easier (by @VitoBarra)
- Now you can see the name the chip you are currently editing (by @VitoBarra)
Fixes
- Ux General Issues #28 (by @VitoBarra)
- Load breaks when loading chips with missing dependency #34 (by @VitoBarra)
- You can't edit chips after renaming them without first restarting the game #36 (by @VitoBarra)
- Bus wires and wire design #31 (by @VitoBarra)
- Pins drift when updating multiple times the same chip #32 (by @VitoBarra)
- Can't import old project from original Digital logic sim #33 (by @VitoBarra)
- UI Bug with Grouped Chips #29 (by @VitoBarra)
- Fixed a typo in the Readme #35 (by @Nicocelot)
Merges
- Merge branch v0.39.0-dev #37
- Clock, Folder Update and Fixes #25 (by @VitoBarra)
- Fixed grammar error #35 (by @Nicocelot)
Contributors
AOx0, VitoBarra, and 2 other contributors
Assets 8
v0.39.0
v0.39.0
We are glad to announce a new version with numerous fixes, expanded features, customizable clock and more.
Huge thanks to @VitoBarra for even making this new version possible and to all contributors.
Everyone is invited to open any Issues, Discussions and PRs to help improve the program.
New features
- New clock chip with customizable Hz (by @VitoBarra)
- Added new feature regarding folders:
- Renaming folders (by @VitoBarra)
- Deleting folders (by @VitoBarra)
- Moving chips between folders (by @VitoBarra)
- Fallback folder to handle compatibility issues (by @VitoBarra)
- Set target FPS or enable vSync from settings (by @AOx0)
Changes
- Reworked the focus system used to handle interaction, now adding a new key-binding option should be easier (by @VitoBarra)
- Now you can see the name the chip you are currently editing (by @VitoBarra)
Fixes
- Ux General Issues #28 (by @VitoBarra)
- Load breaks when loading chips with missing dependency #34 (by @VitoBarra)
- You can't edit chips after renaming them without first restarting the game #36 (by @VitoBarra)
- Bus wires and wire design #31 (by @VitoBarra)
- Pins drift when updating multiple times the same chip #32 (by @VitoBarra)
- Can't import old project from original Digital logic sim #33 (by @VitoBarra)
- UI Bug with Grouped Chips #29 (by @VitoBarra)
- Fixed a typo in the Readme #35 (by @Nicocelot)
Merges
- Merge branch v0.39.0-dev #37
- Clock, Folder Update and Fixes #25 (by @VitoBarra)
- Fixed grammar error #35 (by @Nicocelot)
v0.38
Changes Patch 3 (v0.38)
- Merges New chip dependecy Load System #16
- Merges Enable Vertical Synchronization (VSync) #15
- Fixes chip import button does nothing on Linux build #13
- Fixes #12
- Fixes #14
- Fixes Universal Darwin build not working File Selector.
- And hopefully adds file selector support for ARM Macs. I don't have one for testing.
Changes Patch 2 (v0.37)
Changes Patch 1 (v0.36.1)
v0.36
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome!
v0.37
Changes Patch 2 (v0.37)
Changes Patch 1 (v0.36.1)
v0.36
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome!
v0.36.1
Changes Patch 1 (v0.36.1)
v0.36
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome!
v0.36
New features:
- New chip folder system (by SwissCorePy)
- HDD contents are now persistent (by SwissCorePy)
- You can now zoom and move along the workspace (by SwissCorePy)
- New zoom helper, a minimap of where you are. So you don't get loss while zooming (by SwissCorePy)
- You can now change the scale of the objects in the workplace, allowing to create bigger and more ambitious circuits (by SwissCorePy)
- Bug fixes (by SwissCorePy)
Changes:
- Removed the option hide custom chips from Settings. Now there's a dedicated folder named "Advanced"
- Build performance improvement
- Etc
Features:
- New 4, 8 & 16 bus wires (By t4accer)
- New Run/Stop simulation button (by AOx0)
- Persistent settings (By Tigralt)
- 8x8 display (By Tigralt)
- Edit created chips:
- Button to spawn groups of input/output signal (By sagitarious12)
- New Hard Disk Drive: Its memory is the same across all projects. (By Turnip1234)
- Added hide/show setting to hide built-in chips (except AND & NOT) (by AOx0)
- Some UI tweaks.
Notes:
- Import of chips:
- Does not work on Apple macOS Universal build.
- It may don't work on Silicon Macs, but I don't know since I don't have one for testing.
Huge thanks to SwissCorePy for his work and making possible v0.36 and huge thanks to everyone that has contributed!
There is still a lot of work to do on the current features and lots of options to explore. Any contributions are welcome!