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Commits on Dec 18, 2018

• Avoid using t3 and t4 for supporting RV32E

  zhonghochen

  committedDec 18, 2018
  d943f52

Commits on Dec 3, 2018

• Reduce download size a bit.

  timsifive

  committedDec 3, 2018
  3b90c1f

• Merge pull request riscv-software-src#172 from riscv/downloadtest

  timsifive

  committedDec 3, 2018
  58d61ef

Commits on Nov 30, 2018

• Use more than 1KB for download test.

  timsifive

  committedNov 30, 2018
  9ab668e

Commits on Nov 16, 2018

• Make pylint happy.

  timsifive

  committedNov 16, 2018
  7cc76ea

• Test memory content on failing SC (riscv-software-src#171)

  

  zarubaf

  authored and

  aswaterman

  committedNov 16, 2018
  980711c

Commits on Nov 14, 2018

• Merge pull request riscv-software-src#165 from riscv/flash

  timsifive

  committedNov 14, 2018
  8a2b5bb

• Merge pull request riscv-software-src#169 from riscv/eclipse_memory_read

  cgsfv

  committedNov 14, 2018
  4dc6acb

• Cleanup and renamed test flag to invalid_memory_returns_zero

  cgsfv

  committedNov 14, 2018
  8a46e6b

Commits on Nov 13, 2018

• Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix

  cgsfv

  committedNov 13, 2018
  94a29da

Commits on Nov 12, 2018

• Simpler/more idiomatic way to keep string on stack

  timsifive

  committedNov 12, 2018
  cfab417

Commits on Oct 31, 2018

• Add HiFive1-flash target configuration.

  timsifive

  committedOct 31, 2018
  8312d91

• Fix remaining tests to work from flash:

  timsifive

  committedOct 31, 2018
  b3c5d7a

Commits on Oct 29, 2018

• Almost all tests pass with HiFive1-flash

  timsifive

  committedOct 29, 2018
  ba5ead7

• Tweak debug tests to run out of flash.

  timsifive

  committedOct 29, 2018
  5ee2425

Commits on Oct 24, 2018

• Merge branch 'TriggerLoadAddressInstant'

  timsifive

  committedOct 24, 2018
  ee6c720

• Re-enable TriggerStoreAddressInstant

  timsifive

  committedOct 24, 2018
  cfe78c7

Commits on Oct 5, 2018

• Make HwWatchpoint test fail on incorrect result.

  timsifive

  committedOct 5, 2018
  acc87e1

Commits on Oct 3, 2018

• Added tests for hw and sw watchpoints

  cgsfv

  committedOct 3, 2018
  6ac2c63

Commits on Sep 24, 2018

• bump env

  aswaterman

  committedSep 24, 2018
  fbd7e03

Commits on Sep 13, 2018

• Assert if HiFive1 program is too large.

  timsifive

  committedSep 13, 2018
  f94342b

• Put debug test stack in data instead of text

  timsifive

  committedSep 13, 2018
  a96f32d

Commits on Sep 8, 2018

• Merge branch 'tommythorn-master'

  aswaterman

  committedSep 8, 2018
  0c0d77c

• RV64 s{ll,ra,rl}w tests with non-canonical values

  tommythorn

  committedSep 8, 2018
  ab4f35d

Commits on Sep 7, 2018

• Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (riscv-software-src#158) (riscv-software-src#159)"

  aswaterman

  committedSep 7, 2018
  9d3bc86

Commits on Sep 6, 2018

• breakpoint.S: Don't assume trigger is hardwired to breakpoint (riscv-software-src#158) (riscv-software-src#159)

  

  tommythorn

  authored and

  aswaterman

  committedSep 6, 2018
  901a269

Commits on Sep 3, 2018

• Merge pull request riscv-software-src#156 from riscv/PrivChange

  timsifive

  committedSep 3, 2018
  7906408

Commits on Aug 31, 2018

• Fix CustomRegisterTest.

  timsifive

  committedAug 31, 2018
  705c51e

Commits on Aug 29, 2018

• Add test case for riscv expose_custom.

  timsifive

  committedAug 29, 2018
  4dddbc7

Commits on Aug 28, 2018

• Reset address translation/perms before PrivChange

  timsifive

  committedAug 28, 2018
  ce2b91b

• Neuter TriggerStoreAddressInstant

  timsifive

  committedAug 28, 2018
  40dbc51

Commits on Aug 27, 2018

• Make pylint happy.

  timsifive

  committedAug 27, 2018
  44fd9fd

Commits on Aug 25, 2018

• Temporarily disabling PrivChange test

  aswaterman

  committedAug 25, 2018
  c37ac4c

Commits on Aug 24, 2018

• Make pylint happy with change d1d2d95.

  timsifive

  committedAug 24, 2018
  c0aa8a6

• Get all of the log into the final log file

  timsifive

  committedAug 24, 2018
  3e972b3

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