deps: V8: cherry-pick cb4faa902e9f

Original commit message:

    Reland "[liftoff][arm64] Use 64 bit offset reg in mem op"

    This is a reland of f645d0b857bc669271adcbe95cf25e1554347dd4

    The issue was that converting an i64 to an i32 didn't clear the upper
    bits on arm64. This was not necessary before because we did the zero
    extension as part of the load operand, but this is required now that
    we use the full register.

    Original change's description:
    > [liftoff][arm64] Use 64 bit offset reg in mem op
    >
    > Accessing the Wasm memory with a 64 bit offset was truncated to 32 bit,
    > which is fine if we check bounds first, but not if we rely on the
    > trap handler to catch the OOB.
    >
    > [email protected]
    >
    > Bug: v8:11587
    > Change-Id: I82a3a2906e55d9d640c30e770a5c93532e3a442c
    > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2808942
    > Reviewed-by: Clemens Backes <[email protected]>
    > Commit-Queue: Thibaud Michaud <[email protected]>
    > Cr-Commit-Position: refs/heads/master@{#73829}

    Bug: v8:11587
    Change-Id: Ibc182475745c6f697a0ba6d75c260b74ddf8fe52
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2810846
    Reviewed-by: Clemens Backes <[email protected]>
    Commit-Queue: Thibaud Michaud <[email protected]>
    Cr-Commit-Position: refs/heads/master@{#73853}

Refs: v8/v8@cb4faa9

PR-URL: nodejs#39337
Reviewed-By: Matteo Collina <[email protected]>
Reviewed-By: James M Snell <[email protected]>

common.gypi

@@ -36,7 +36,7 @@
 
     # Reset this number to 0 on major V8 upgrades.
     # Increment by one for each non-official patch applied to deps/v8.
-    'v8_embedder_string': '-node.13',
+    'v8_embedder_string': '-node.14',
 
     ##### V8 defaults for Node.js #####
 

deps/v8/src/wasm/baseline/arm64/liftoff-assembler-arm64.h

@@ -128,7 +128,7 @@ inline MemOperand GetMemOp(LiftoffAssembler* assm,
                            UseScratchRegisterScope* temps, Register addr,
                            Register offset, T offset_imm) {
   if (offset.is_valid()) {
-    if (offset_imm == 0) return MemOperand(addr.X(), offset.W(), UXTW);
+    if (offset_imm == 0) return MemOperand(addr.X(), offset.X());
     Register tmp = temps->AcquireX();
     DCHECK_GE(kMaxUInt32, offset_imm);
     assm->Add(tmp, offset.X(), offset_imm);
@@ -1333,7 +1333,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
                                             LiftoffRegister src, Label* trap) {
   switch (opcode) {
     case kExprI32ConvertI64:
-      if (src != dst) Mov(dst.gp().W(), src.gp().W());
+      Mov(dst.gp().W(), src.gp().W());
       return true;
     case kExprI32SConvertF32:
       Fcvtzs(dst.gp().W(), src.fp().S());  // f32 -> i32 round to zero.