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SoC: Add sw drivers for hbirdv2 peripheral
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@hucan7
hucan7 committed Jul 20, 2020
1 parent 71932f5 commit bca62ad
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Showing 13 changed files with 728 additions and 304 deletions.
3 changes: 3 additions & 0 deletions SoC/hbirdv2/Common/Include/hbird_sdk_soc.h
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Expand Up @@ -9,6 +9,9 @@
#include "hbirdv2.h"
#include "hbirdv2_uart.h"
#include "hbirdv2_gpio.h"
#include "hbirdv2_i2c.h"
#include "hbirdv2_spi.h"
#include "hbirdv2_pwm.h"

#ifdef __cplusplus
}
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251 changes: 141 additions & 110 deletions SoC/hbirdv2/Common/Include/hbirdv2.h
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Original file line number Diff line number Diff line change
Expand Up @@ -232,47 +232,6 @@ typedef enum EXCn {
/****************************************************************************
* Platform definitions
*****************************************************************************/
// IOF Mappings
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
#define SPI11_NUM_SS (4)
#define IOF_SPI1_SS0 (2u)
#define IOF_SPI1_SS1 (8u)
#define IOF_SPI1_SS2 (9u)
#define IOF_SPI1_SS3 (10u)
#define IOF_SPI1_MOSI (3u)
#define IOF_SPI1_MISO (4u)
#define IOF_SPI1_SCK (5u)
#define IOF_SPI1_DQ0 (3u)
#define IOF_SPI1_DQ1 (4u)
#define IOF_SPI1_DQ2 (6u)
#define IOF_SPI1_DQ3 (7u)

#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
#define SPI2_NUM_SS (1)
#define IOF_SPI2_SS0 (26u)
#define IOF_SPI2_MOSI (27u)
#define IOF_SPI2_MISO (28u)
#define IOF_SPI2_SCK (29u)
#define IOF_SPI2_DQ0 (27u)
#define IOF_SPI2_DQ1 (28u)
#define IOF_SPI2_DQ2 (30u)
#define IOF_SPI2_DQ3 (31u)

#define IOF0_UART0_MASK _AC(0x00030000, UL)
#define IOF_UART0_RX (16u)
#define IOF_UART0_TX (17u)

#define IOF0_UART1_MASK _AC(0x03000000, UL)
#define IOF_UART1_RX (24u)
#define IOF_UART1_TX (25u)

#define IOF0_I2C_MASK _AC(0x00003000, UL)
#define IOF_I2C_SDA (12u)
#define IOF_I2C_SCL (13u)

#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)

// Interrupt Numbers
#define SOC_PLIC_NUM_INTERRUPTS 32
Expand All @@ -289,53 +248,39 @@ typedef enum EXCn {
* @brief GPIO
*/
typedef struct { /*!< GPIO Structure */
__IOM uint32_t INPUT_VAL;
__IOM uint32_t INPUT_EN;
__IOM uint32_t OUTPUT_EN;
__IOM uint32_t OUTPUT_VAL;
__IOM uint32_t PULLUP_EN;
__IOM uint32_t DRIVE;
__IOM uint32_t RISE_IE;
__IOM uint32_t RISE_IP;
__IOM uint32_t FALL_IE;
__IOM uint32_t FALL_IP;
__IOM uint32_t HIGH_IE;
__IOM uint32_t HIGH_IP;
__IOM uint32_t LOW_IE;
__IOM uint32_t LOW_IP;
__IOM uint32_t IOF_EN;
__IOM uint32_t IOF_SEL;
__IOM uint32_t OUTPUT_XOR;
__IOM uint32_t PADDIR;
__IOM uint32_t PADIN;
__IOM uint32_t PADOUT;
__IOM uint32_t INTEN;
__IOM uint32_t INTTYPE0;
__IOM uint32_t INTTYPE1;
__IOM uint32_t INTSTATUS;
} GPIO_TypeDef;

/**
* @brief UART
*/
typedef struct {
__IOM uint32_t TXFIFO;
__IOM uint32_t RXFIFO;
__IOM uint32_t TXCTRL;
__IOM uint32_t RXCTRL;
__IOM uint32_t IE;
__IOM uint32_t IP;
__IOM uint32_t DIV;
union {
__IOM uint32_t RBR;
__IOM uint32_t DLL;
__IOM uint32_t THR;
};
union {
__IOM uint32_t DLM;
__IOM uint32_t IER;
};
union {
__IOM uint32_t IIR;
__IOM uint32_t FCR;
};
__IOM uint32_t LCR;
__IOM uint32_t MCR;
__IOM uint32_t LSR;
__IOM uint32_t MSR;
__IOM uint32_t SCR;
} UART_TypeDef;

/**
* @brief PWM
*/
typedef struct {
__IOM uint32_t CFG;
uint32_t RESERVED0;
__IOM uint32_t COUNT;
uint32_t RESERVED1;
__IOM uint32_t S;
uint32_t RESERVED2[3];
__IOM uint32_t CMP0;
__IOM uint32_t CMP1;
__IOM uint32_t CMP2;
__IOM uint32_t CMP3;
} PWM_TypeDef;

/**
* @brief QSPI
Expand Down Expand Up @@ -365,17 +310,117 @@ typedef struct {
__IOM uint32_t IP;
} QSPI_TypeDef;

/**
* @brief SPI
*/
typedef struct {
__IOM uint32_t STATUS;
__IOM uint32_t CLKDIV;
__IOM uint32_t SPICMD;
__IOM uint32_t SPIADR;
__IOM uint32_t SPILEN;
__IOM uint32_t SPIDUM;
__IOM uint32_t TXFIFO;
__IOM uint32_t Pad;
__IOM uint32_t RXFIFO;
__IOM uint32_t INTCFG;
__IOM uint32_t INTSTA;
} SPI_TypeDef;

/**
* @brief I2C
*/
typedef struct {
__IOM uint8_t PRERlo;
__IOM uint8_t PRERhi;
__IOM uint8_t CTR;
__IOM uint8_t TXRXR; /* TXR and RXR in same address */
__IOM uint8_t CSR; /* CR and SR in same address */
__IOM uint32_t PRE;
__IOM uint32_t CTR;
__IOM uint32_t RX;
__IOM uint32_t STATUS;
__IOM uint32_t TX;
__IOM uint32_t CMD;
} I2C_TypeDef;

/**
* @brief PWM
*/

typedef enum {
PWM_TIMER0=0,
PWM_TIMER1=1,
PWM_TIMER2=2,
PWM_TIMER3=3,
} PwmTimerNum;

typedef enum {
PWM_TIMER_TH_CHANNEL0=0,
PWM_TIMER_TH_CHANNEL1=1,
PWM_TIMER_TH_CHANNEL2=2,
PWM_TIMER_TH_CHANNEL3=3,
} PwmTimerThChannel;

enum{
pwm_timer_event0 = 0,
pwm_timer_event1 ,
pwm_timer_event2 ,
pwm_timer_event3 ,
};

typedef enum {
PWM_TIMER_CMD_START = 0x01, /* Start counting */
PWM_TIMER_CMD_STOP = 0x02, /* Stop counting */
PWM_TIMER_CMD_UPD = 0x04, /* Update timer params */
PWM_TIMER_CMD_RST = 0x08, /* Reset counter value */
} PwmCounterCmd;

typedef struct {
unsigned int SelectInputSource:8; /* Select counting condition */
unsigned int InputEnableIn:3; /* Define enable rules:
000, always count (use clock)
001 count when external input is 0
010 count when external input is 1
011 count on rising edge of external
100 count on falling edge of external
101 count on falling and on rising edge of external
*/
unsigned int FllOrRTC:1; /* Clock input of counter is Fll or RTC */
unsigned int IncThenDec:1; /* When counter reaches threshold count down if IncThenDec else return to 0 and ocunt up again */
unsigned int Pad:3;
unsigned int PreScaler:8; /* */
unsigned int Pad2:8;
} PwmCounterConfig;

typedef struct {
unsigned int chThreshold:16; /* Threshold value for the channel of a counter */
unsigned int chAction:3;
/* When counter reaches threshold:
000: Set
001: Toggle then next is Clear
010: Set then Clear
011: Toggle
100: Clear
101: Toggle then next is Set
110: Clear then Set
*/
unsigned int Pad:13;
} PwmChannelThConfig;


typedef struct{
unsigned int evt0_sel:4;
unsigned int evt1_sel:4;
unsigned int evt2_sel:4;
unsigned int evt3_sel:4;
unsigned int evt_en:4;
unsigned int pad:12;
} PwmTimerEvt;

typedef union{
PwmCounterConfig timerConf;
unsigned int timerTh; /* Threshold value for the counter */
PwmChannelThConfig ch_ThConfig;
PwmTimerEvt timerEvt;
unsigned int Raw;
} pwm_timer;

/*@}*/ /* end of group hbird_Peripherals */


Expand Down Expand Up @@ -405,18 +450,12 @@ typedef struct {
#define HBIRD_PERIPH_BASE (0x10000000UL) /*!< (Peripheral) Base Address */

/* Peripheral memory map */
/* Fast-IO Interfaced IP */
#define GPIO_BASE (HBIRD_PERIPH_BASE + 0x12000) /*!< (GPIO) Base Address */
/* PPI Interfaced IP */
#define UART0_BASE (HBIRD_PERIPH_BASE + 0x13000) /*!< (UART0) Base Address */
#define QSPI0_BASE (HBIRD_PERIPH_BASE + 0x14000) /*!< (QSPI0) Base Address */
#define PWM0_BASE (HBIRD_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */
#define UART1_BASE (HBIRD_PERIPH_BASE + 0x23000) /*!< (UART1) Base Address */
#define QSPI1_BASE (HBIRD_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */
#define PWM1_BASE (HBIRD_PERIPH_BASE + 0x25000) /*!< (PWM1) Base Address */
#define QSPI2_BASE (HBIRD_PERIPH_BASE + 0x34000) /*!< (QSPI2) Base Address */
#define PWM2_BASE (HBIRD_PERIPH_BASE + 0x35000) /*!< (PWM2) Base Address */
#define I2C_BASE (HBIRD_PERIPH_BASE + 0x42000) /*!< (I2C Master) Base Address */
#define PWM_BASE (HBIRD_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */
#define SPI1_BASE (HBIRD_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */
#define I2C_BASE (HBIRD_PERIPH_BASE + 0x25000) /*!< (I2C Master) Base Address */

/** @} */ /* End of group Device_Peripheral_peripheralAddr */

Expand All @@ -434,29 +473,21 @@ typedef struct {
#define GPIO ((GPIO_TypeDef *) GPIO_BASE)
#define UART0 ((UART_TypeDef *) UART0_BASE)
#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE)
#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
#define UART1 ((UART_TypeDef *) UART1_BASE)
#define QSPI1 ((QSPI_TypeDef *) QSPI1_BASE)
#define PWM1 ((PWM_TypeDef *) PWM1_BASE)
#define QSPI2 ((QSPI_TypeDef *) QSPI2_BASE)
#define PWM2 ((PWM_TypeDef *) PWM2_BASE)
#define I2C ((I2C_TypeDef *) I2C_BASE)
#define PWM ((PWM_TypeDef *) PWM_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define I2C ((I2C_TypeDef *) I2C_BASE)

// Helper functions
#define _REG8(p, i) (*(volatile uint8_t *) ((p) + (i)))
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))

#define GPIO_REG(offset) _REG32(GPIO_BASE, offset)
#define PWM0_REG(offset) _REG32(PWM0_BASE, offset)
#define PWM1_REG(offset) _REG32(PWM1_BASE, offset)
#define PWM2_REG(offset) _REG32(PWM2_BASE, offset)
#define SPI0_REG(offset) _REG32(QSPI0_BASE, offset)
#define SPI1_REG(offset) _REG32(QSPI1_BASE, offset)
#define SPI2_REG(offset) _REG32(QSPI2_BASE, offset)
#define GPIO_REG(offset) _REG32(GPIO_BASE, offset)
#define PWM_REG(offset) _REG32(PWM_BASE, offset)
#define QSPI0_REG(offset) _REG32(QSPI0_BASE, offset)
#define SPI1_REG(offset) _REG32(SPI1_BASE, offset)
#define UART0_REG(offset) _REG32(UART0_BASE, offset)
#define UART1_REG(offset) _REG32(UART1_BASE, offset)
#define I2C_REG(offset) _REG8(I2C_BASE, offset)
#define I2C_REG(offset) _REG8(I2C_BASE, offset)

// Misc

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38 changes: 5 additions & 33 deletions SoC/hbirdv2/Common/Include/hbirdv2_gpio.h
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Original file line number Diff line number Diff line change
@@ -1,56 +1,28 @@
// See LICENSE for license details.
#ifndef _HBIRD_GPIO_H
#define _HBIRD_GPIO_H
#ifndef _HBIRDV2_GPIO_H
#define _HBIRDV2_GPIO_H

#ifdef __cplusplus
extern "C" {
#endif

#define GPIO_INPUT_VAL (0x00)
#define GPIO_INPUT_EN (0x04)
#define GPIO_OUTPUT_EN (0x08)
#define GPIO_OUTPUT_VAL (0x0C)
#define GPIO_PULLUP_EN (0x10)
#define GPIO_DRIVE (0x14)
#define GPIO_RISE_IE (0x18)
#define GPIO_RISE_IP (0x1C)
#define GPIO_FALL_IE (0x20)
#define GPIO_FALL_IP (0x24)
#define GPIO_HIGH_IE (0x28)
#define GPIO_HIGH_IP (0x2C)
#define GPIO_LOW_IE (0x30)
#define GPIO_LOW_IP (0x34)
#define GPIO_IOF_EN (0x38)
#define GPIO_IOF_SEL (0x3C)
#define GPIO_OUTPUT_XOR (0x40)

typedef enum iof_func {
IOF_SEL_GPIO = 0,
IOF_SEL_0 = 1,
IOF_SEL_1 = 2
} IOF_FUNC;

typedef enum gpio_int_type {
GPIO_INT_RISE = 0,
GPIO_INT_FALL = 1,
GPIO_INT_HIGH = 2,
GPIO_INT_LOW = 3
} GPIO_INT_TYPE;

int32_t gpio_iof_config(GPIO_TypeDef *gpio, uint32_t mask, IOF_FUNC func);
int32_t gpio_enable_output(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_enable_input(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_write(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_toggle(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_read(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_set_pue(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_set_ds(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_set_outxor(GPIO_TypeDef *gpio, uint32_t mask, uint32_t value);
int32_t gpio_enable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_disable_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_clear_interrupt(GPIO_TypeDef *gpio, uint32_t mask, GPIO_INT_TYPE type);
int32_t gpio_disable_interrupt(GPIO_TypeDef *gpio, uint32_t mask);
int32_t gpio_clear_interrupt(GPIO_TypeDef *gpio, uint32_t mask);

#ifdef __cplusplus
}
#endif
#endif /* _HBIRD_GPIO_H */
#endif /* _HBIRDV2_GPIO_H */
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