Code style updates.

ppci/arch/__init__.py

@@ -42,7 +42,7 @@ def get_current_arch():
 
 
 def get_arch(arch):
-    """ Try to return an architecture instance.
+    """Try to return an architecture instance.
 
     Args:
         arch: can be a string in the form of arch:option1:option2

ppci/arch/arch.py

@@ -44,7 +44,7 @@ class Architecture(MachineArchitecture):
     """ Base class for all targets """
 
     def __init__(self, options=None):
-        """ Create a new machine instance.
+        """Create a new machine instance.
 
         Arguments:
             options: a tuple with which options to enable.
@@ -85,7 +85,7 @@ def move(self, dst, src):  # pragma: no cover
 
     @abc.abstractmethod
     def gen_prologue(self, frame):  # pragma: no cover
-        """ Generate instructions for the epilogue of a frame.
+        """Generate instructions for the epilogue of a frame.
 
         Arguments:
             frame: the function frame for which to create a prologue
@@ -94,7 +94,7 @@ def gen_prologue(self, frame):  # pragma: no cover
 
     @abc.abstractmethod
     def gen_epilogue(self, frame):  # pragma: no cover
-        """ Generate instructions for the epilogue of a frame.
+        """Generate instructions for the epilogue of a frame.
 
         Arguments:
             frame: the function frame for which to create a prologue
@@ -108,7 +108,7 @@ def gen_call(self, frame, label, args, rv):  # pragma: no cover
 
     @abc.abstractmethod
     def gen_function_enter(self, args):  # pragma: no cover
-        """ Generate code to extract arguments from the proper locations
+        """Generate code to extract arguments from the proper locations
 
         The default implementation tries to use registers and move
         instructions.
@@ -134,8 +134,8 @@ def determine_arg_locations(self, arg_types):  # pragma: no cover
 
     @abc.abstractmethod
     def determine_rv_location(self, ret_type):  # pragma: no cover
-        """ Determine the location of a return value of a function given the
-        type of return value """
+        """Determine the location of a return value of a function given the
+        type of return value"""
         raise NotImplementedError("Implement this")
 
     def get_reloc(self, name):
@@ -152,14 +152,14 @@ def get_runtime(self):
 
     @lru_cache(maxsize=30)
     def get_compiler_rt_lib(self):
-        """ Gets the runtime for the compiler. Returns an object with the
-        compiler runtime for this architecture """
+        """Gets the runtime for the compiler. Returns an object with the
+        compiler runtime for this architecture"""
         return self.get_runtime()
 
     runtime = property(get_compiler_rt_lib)
 
     def get_reloc_type(self, reloc_type, symbol):
-        """ Re-implement this function to support ELF format
+        """Re-implement this function to support ELF format
         relocations.
         """
-        raise NotImplementedError('ELF format relocations')
+        raise NotImplementedError("ELF format relocations")

ppci/arch/arch_info.py

@@ -81,7 +81,7 @@ def get_alignment(self, typ):
         return self.get_type_info(typ).alignment
 
     def calc_alias(self):
-        """ Calculate a complete overview of register aliasing.
+        """Calculate a complete overview of register aliasing.
 
         This uses the alias attribute when a register is
         defined.
@@ -106,7 +106,7 @@ def calc_alias(self):
 
 
 def dfs_alias(register):
-    """ Do a depth first search on the aliases member.
+    """Do a depth first search on the aliases member.
 
     This can be used to find aliases of aliases.
     """

ppci/arch/arm/arch.py

@@ -109,7 +109,7 @@ def move(self, dst, src):
             )
 
     def gen_prologue(self, frame):
-        """ Returns prologue instruction sequence.
+        """Returns prologue instruction sequence.
 
         Reserve stack for this calling frame for:
 
@@ -167,7 +167,7 @@ def gen_prologue(self, frame):
                 yield arm_instructions.SubImm(SP, SP, ssize)
 
     def gen_epilogue(self, frame):
-        """ Return epilogue sequence for a frame.
+        """Return epilogue sequence for a frame.
 
         Adjust frame pointer and add constant pool.
 
@@ -312,7 +312,9 @@ def gen_function_enter(self, args):
         arg_types = [a[0] for a in args]
         arg_locs = self.determine_arg_locations(arg_types)
 
-        arg_regs = set(l for l in arg_locs if isinstance(l, ArmRegister))
+        arg_regs = set(
+            arg_loc for arg_loc in arg_locs if isinstance(arg_loc, ArmRegister)
+        )
         yield RegisterUseDef(defs=arg_regs)
 
         for arg_loc, arg2 in zip(arg_locs, args):
@@ -359,13 +361,13 @@ def between_blocks(self, frame):
 
     def determine_arg_locations(self, arg_types):
         """
-            Given a set of argument types, determine location for argument
-            ABI:
-            pass arg1 in R1
-            pass arg2 in R2
-            pass arg3 in R3
-            pass arg4 in R4
-            return value in R0
+        Given a set of argument types, determine location for argument
+        ABI:
+        pass arg1 in R1
+        pass arg2 in R2
+        pass arg3 in R3
+        pass arg4 in R4
+        return value in R0
         """
         # TODO: what ABI to use?
         # Perhaps follow the arm ABI spec?

ppci/arch/arm/arm_instructions.py

@@ -191,10 +191,10 @@ def encode(self):
 
 
 class Sdiv(ArmInstruction):
-    """ Encoding A1
-        rd = rn / rm
+    """Encoding A1
+    rd = rn / rm
 
-        This instruction is not always present
+    This instruction is not always present
     """
 
     rd = Operand("rd", ArmRegister, write=True)
@@ -215,8 +215,8 @@ def encode(self):
 
 
 class Udiv(ArmInstruction):
-    """ Encoding A1
-        rd = rn / rm
+    """Encoding A1
+    rd = rn / rm
     """
 
     rd = Operand("rd", ArmRegister, write=True)
@@ -238,9 +238,9 @@ def encode(self):
 
 
 class Mls(ArmInstruction):
-    """ Multiply substract
-        Semantics:
-        rd = ra - rn * rm
+    """Multiply substract
+    Semantics:
+    rd = ra - rn * rm
     """
 
     rd = Operand("rd", ArmRegister, write=True)
@@ -644,7 +644,7 @@ class Ldrb(LdrStrBase):
 
 
 class Ldrsb(ArmInstruction):
-    """ ldrsb rt, [rn, offset].
+    """ldrsb rt, [rn, offset].
 
     Load byte and sign extend.
     """
@@ -678,7 +678,7 @@ def encode(self):
 
 
 class Ldrh_imm(ArmInstruction):
-    """ ldrh rt, [rn, offset].
+    """ldrh rt, [rn, offset].
 
     Load half word and zero extend.
     """
@@ -712,7 +712,7 @@ def encode(self):
 
 
 class Ldrsh_imm(ArmInstruction):
-    """ ldrsh rt, [rn, offset].
+    """ldrsh rt, [rn, offset].
 
     Load signed half word and sign extend.
     """
@@ -746,7 +746,7 @@ def encode(self):
 
 
 class Ldrsh_reg(ArmInstruction):
-    """ ldrsh rt, [rn, rm].
+    """ldrsh rt, [rn, rm].
 
     Load signed half word and sign extend.
     """
@@ -793,9 +793,9 @@ def encode(self):
 
 
 class Ldr3(ArmInstruction):
-    """ Load PC relative constant value
-        LDR rt, label
-        encoding A1
+    """Load PC relative constant value
+    LDR rt, label
+    encoding A1
     """
 
     rt = Operand("rt", ArmRegister, write=True)

ppci/arch/arm/thumb_instructions.py

@@ -15,8 +15,7 @@
 
 
 class ThumbInstruction(Instruction):
-    """ Base of all thumb instructions.
-    """
+    """Base of all thumb instructions."""
 
     tokens = [ThumbToken]
     isa = thumb_isa
@@ -437,10 +436,10 @@ def encode(self):
 
 class Mul(ThumbInstruction):
     """
-        mul Rn, Rdm
+    mul Rn, Rdm
 
-        multiply Rn and Rm and store the result in Rd
-        Rd and Rm are the same register.
+    multiply Rn and Rm and store the result in Rd
+    Rd and Rm are the same register.
     """
 
     rn = Operand("rn", LowArmRegister, read=True)
@@ -458,8 +457,8 @@ def encode(self):
 
 
 class Sdiv(LongThumbInstruction):
-    """ Signed division.
-        Encoding T1
+    """Signed division.
+    Encoding T1
     """
 
     rd = Operand("rd", ArmRegister, write=True)
@@ -542,8 +541,8 @@ def relocations(self):
 
 
 class Bw(LongThumbInstruction):
-    """ Encoding T4
-        Same encoding as Bl, longer jumps are possible with this function!
+    """Encoding T4
+    Same encoding as Bl, longer jumps are possible with this function!
     """
 
     target = Operand("target", str)

ppci/arch/avr/arch.py

@@ -203,8 +203,8 @@ def gen_prologue(self, frame):
             yield Adiw(Y, 1)
 
     def gen_epilogue(self, frame):
-        """ Return epilogue sequence for a frame. Adjust frame pointer
-            and add constant pool
+        """Return epilogue sequence for a frame. Adjust frame pointer
+        and add constant pool
         """
         if frame.stacksize > 0:
             # Pop x times to adjust stack:

ppci/arch/avr/instructions.py

@@ -593,8 +593,8 @@ class Out(AvrInstruction):
 
 
 class PseudoAvrInstruction(ArtificialInstruction):
-    """ These instructions are used to implement word arithmatic that is
-        actually implemented by two 8-bit registers """
+    """These instructions are used to implement word arithmatic that is
+    actually implemented by two 8-bit registers"""
 
     pass