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[AMDGPU][AsmParser][NFC] Simplify instruction operand definitions.
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This addresses the trivial cases that only require removing the
operand classes and renaming related entities.

Part of <llvm/llvm-project#62629>.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D153965
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@kosarev @veselypeta
kosarev authored and veselypeta committed Sep 2, 2024
2 parents 1465f16 + 59fd48d commit 4e2c859
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Showing 6 changed files with 35 additions and 100 deletions.
28 changes: 12 additions & 16 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -864,7 +864,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {

bool isSWaitCnt() const;
bool isDepCtr() const;
bool isSDelayAlu() const;
bool isSDelayALU() const;
bool isHwreg() const;
bool isSendMsg() const;
bool isSwizzle() const;
Expand Down Expand Up @@ -1602,14 +1602,14 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
void cvtExp(MCInst &Inst, const OperandVector &Operands);

bool parseCnt(int64_t &IntVal);
OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
OperandMatchResultTy parseSWaitCnt(OperandVector &Operands);

bool parseDepCtr(int64_t &IntVal, unsigned &Mask);
void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);
OperandMatchResultTy parseDepCtrOps(OperandVector &Operands);
OperandMatchResultTy parseDepCtr(OperandVector &Operands);

bool parseDelay(int64_t &Delay);
OperandMatchResultTy parseSDelayAluOps(OperandVector &Operands);
OperandMatchResultTy parseSDelayALU(OperandVector &Operands);

OperandMatchResultTy parseHwreg(OperandVector &Operands);

Expand Down Expand Up @@ -1723,7 +1723,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
unsigned MCK);

OperandMatchResultTy parseExpTgt(OperandVector &Operands);
OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
OperandMatchResultTy parseSendMsg(OperandVector &Operands);
OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
Expand All @@ -1738,7 +1738,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const unsigned MinVal,
const unsigned MaxVal,
const StringRef ErrMsg);
OperandMatchResultTy parseSwizzleOp(OperandVector &Operands);
OperandMatchResultTy parseSwizzle(OperandVector &Operands);
bool parseSwizzleOffset(int64_t &Imm);
bool parseSwizzleMacro(int64_t &Imm);
bool parseSwizzleQuadPerm(int64_t &Imm);
Expand Down Expand Up @@ -6588,8 +6588,7 @@ bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
return true;
}

OperandMatchResultTy
AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
OperandMatchResultTy AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {
AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
int64_t Waitcnt = getWaitcntBitMask(ISA);
SMLoc S = getLoc();
Expand Down Expand Up @@ -6670,8 +6669,7 @@ bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {
return true;
}

OperandMatchResultTy
AMDGPUAsmParser::parseSDelayAluOps(OperandVector &Operands) {
OperandMatchResultTy AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {
int64_t Delay = 0;
SMLoc S = getLoc();

Expand All @@ -6694,7 +6692,7 @@ AMDGPUOperand::isSWaitCnt() const {
return isImm();
}

bool AMDGPUOperand::isSDelayAlu() const { return isImm(); }
bool AMDGPUOperand::isSDelayALU() const { return isImm(); }

//===----------------------------------------------------------------------===//
// DepCtr
Expand Down Expand Up @@ -6758,7 +6756,7 @@ bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {
return true;
}

OperandMatchResultTy AMDGPUAsmParser::parseDepCtrOps(OperandVector &Operands) {
OperandMatchResultTy AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {
using namespace llvm::AMDGPU::DepCtr;

int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());
Expand Down Expand Up @@ -6972,8 +6970,7 @@ AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,
return true;
}

OperandMatchResultTy
AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
OperandMatchResultTy AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {
using namespace llvm::AMDGPU::SendMsg;

int64_t ImmVal = 0;
Expand Down Expand Up @@ -7567,8 +7564,7 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
return false;
}

OperandMatchResultTy
AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) {
OperandMatchResultTy AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {
SMLoc S = getLoc();
int64_t Imm = 0;

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/DSInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -631,7 +631,7 @@ def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
} // End SubtargetPredicate = HasDsSrc2Insts

let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, Swizzle>;
}

let mayStore = 0 in {
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1277,9 +1277,9 @@ void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
O << '.' << "xyzw"[Chan & 0x3];
}

void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
using namespace llvm::AMDGPU::VGPRIndexMode;
unsigned Val = MI->getOperand(OpNo).getImm();

Expand Down Expand Up @@ -1486,7 +1486,7 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
}
}

void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
void AMDGPUInstPrinter::printSWaitCnt(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
Expand Down Expand Up @@ -1548,7 +1548,7 @@ void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
}
}

void AMDGPUInstPrinter::printDelayFlag(const MCInst *MI, unsigned OpNo,
void AMDGPUInstPrinter::printSDelayALU(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const char *BadInstId = "/* invalid instid value */";
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -165,8 +165,8 @@ class AMDGPUInstPrinter : public MCInstPrinter {
void printInterpAttrChan(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);

void printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printGPRIdxMode(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printMemOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
Expand Down Expand Up @@ -240,11 +240,11 @@ class AMDGPUInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printWaitFlag(const MCInst *MI, unsigned OpNo,
void printSWaitCnt(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printDelayFlag(const MCInst *MI, unsigned OpNo,
void printSDelayALU(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
Expand Down
60 changes: 5 additions & 55 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -943,72 +943,22 @@ def InterpAttr : CustomOperand<i32>;

def InterpAttrChan : ImmOperand<i32>;

def SendMsgMatchClass : AsmOperandClass {
let Name = "SendMsg";
let PredicateMethod = "isSendMsg";
let ParserMethod = "parseSendMsgOp";
let RenderMethod = "addImmOperands";
}

def SwizzleMatchClass : AsmOperandClass {
let Name = "Swizzle";
let PredicateMethod = "isSwizzle";
let ParserMethod = "parseSwizzleOp";
let RenderMethod = "addImmOperands";
let IsOptional = 1;
}

def SWaitMatchClass : AsmOperandClass {
let Name = "SWaitCnt";
let RenderMethod = "addImmOperands";
let ParserMethod = "parseSWaitCntOps";
}

def DepCtrMatchClass : AsmOperandClass {
let Name = "DepCtr";
let RenderMethod = "addImmOperands";
let ParserMethod = "parseDepCtrOps";
}

def SDelayMatchClass : AsmOperandClass {
let Name = "SDelayAlu";
let RenderMethod = "addImmOperands";
let ParserMethod = "parseSDelayAluOps";
}

def VReg32OrOffClass : AsmOperandClass {
let Name = "VReg32OrOff";
let ParserMethod = "parseVReg32OrOff";
}

let OperandType = "OPERAND_IMMEDIATE" in {
def SendMsgImm : Operand<i32> {
let PrintMethod = "printSendMsg";
let ParserMatchClass = SendMsgMatchClass;
}
def SendMsg : CustomOperand<i32>;

def SwizzleImm : Operand<i16> {
let PrintMethod = "printSwizzle";
let ParserMatchClass = SwizzleMatchClass;
}
def Swizzle : CustomOperand<i16, 1>;

def Endpgm : CustomOperand<i16, 1>;

def WAIT_FLAG : Operand <i32> {
let ParserMatchClass = SWaitMatchClass;
let PrintMethod = "printWaitFlag";
}
def SWaitCnt : CustomOperand<i32>;

def DepCtrImm : Operand <i32> {
let ParserMatchClass = DepCtrMatchClass;
let PrintMethod = "printDepCtr";
}
def DepCtr : CustomOperand<i32>;

def DELAY_FLAG : Operand <i32> {
let ParserMatchClass = SDelayMatchClass;
let PrintMethod = "printDelayFlag";
}
} // End OperandType = "OPERAND_IMMEDIATE"
def SDelayALU : CustomOperand<i32>;

include "SIInstrFormats.td"
include "VIInstrFormats.td"
Expand Down
27 changes: 8 additions & 19 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -6,18 +6,7 @@
//
//===----------------------------------------------------------------------===//

def GPRIdxModeMatchClass : AsmOperandClass {
let Name = "GPRIdxMode";
let PredicateMethod = "isGPRIdxMode";
let ParserMethod = "parseGPRIdxMode";
let RenderMethod = "addImmOperands";
}

def GPRIdxMode : Operand<i32> {
let PrintMethod = "printVGPRIndexMode";
let ParserMatchClass = GPRIdxModeMatchClass;
let OperandType = "OPERAND_IMMEDIATE";
}
def GPRIdxMode : CustomOperand<i32>;

class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps,
list<dag> pattern=[]> :
Expand Down Expand Up @@ -402,11 +391,11 @@ let SubtargetPredicate = isGFX11Plus in {
// For s_sendmsg_rtn_* the src0 field encodes the message type directly; it
// is not an SGPR number.
def S_SENDMSG_RTN_B32 : SOP1_Pseudo<
"s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsgImm:$src0),
"s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsg:$src0),
"$sdst, $src0", [(set i32:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]
>;
def S_SENDMSG_RTN_B64 : SOP1_Pseudo<
"s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsgImm:$src0),
"s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsg:$src0),
"$sdst, $src0", [(set i64:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]
>;
}
Expand Down Expand Up @@ -1284,7 +1273,7 @@ def S_WAKEUP : SOPP_Pseudo <"s_wakeup", (ins) > {
}

let hasSideEffects = 1 in
def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins WAIT_FLAG:$simm16), "$simm16",
def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins SWaitCnt:$simm16), "$simm16",
[(int_amdgcn_s_waitcnt timm:$simm16)]>;
def S_SETHALT : SOPP_Pseudo <"s_sethalt" , (ins i32imm:$simm16), "$simm16",
[(int_amdgcn_s_sethalt timm:$simm16)]>;
Expand All @@ -1305,12 +1294,12 @@ def S_SETPRIO : SOPP_Pseudo <"s_setprio", (ins i16imm:$simm16), "$simm16",
}

let Uses = [EXEC, M0] in {
def S_SENDMSG : SOPP_Pseudo <"s_sendmsg" , (ins SendMsgImm:$simm16), "$simm16",
def S_SENDMSG : SOPP_Pseudo <"s_sendmsg" , (ins SendMsg:$simm16), "$simm16",
[(int_amdgcn_s_sendmsg (i32 timm:$simm16), M0)]> {
let hasSideEffects = 1;
}

def S_SENDMSGHALT : SOPP_Pseudo <"s_sendmsghalt" , (ins SendMsgImm:$simm16), "$simm16",
def S_SENDMSGHALT : SOPP_Pseudo <"s_sendmsghalt" , (ins SendMsg:$simm16), "$simm16",
[(int_amdgcn_s_sendmsghalt (i32 timm:$simm16), M0)]> {
let hasSideEffects = 1;
}
Expand Down Expand Up @@ -1367,7 +1356,7 @@ let SubtargetPredicate = isGFX10Plus in {
let fixed_imm = 1;
}
def S_WAITCNT_DEPCTR :
SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtrImm:$simm16), "$simm16">;
SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtr:$simm16), "$simm16">;

let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {
def S_ROUND_MODE :
Expand All @@ -1386,7 +1375,7 @@ let SubtargetPredicate = isGFX11Plus in {
"$simm16"> {
let hasSideEffects = 1;
}
def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins DELAY_FLAG:$simm16),
def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins SDelayALU:$simm16),
"$simm16">;
} // End SubtargetPredicate = isGFX11Plus

Expand Down

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