A High-performance Timing Analysis Tool for VLSI Systems
-
Updated
May 26, 2023 - Verilog
A High-performance Timing Analysis Tool for VLSI Systems
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
5 Day TCL begginer to advanced training workshop by VSD
A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)
TCL Script automating the frontend of ASIC design
5-Day TCL begginer to advanced workshop by VSD
CAD in NYCU
This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).
Add a description, image, and links to the static-timing-analysis topic page so that developers can more easily learn about it.
To associate your repository with the static-timing-analysis topic, visit your repo's landing page and select "manage topics."