usb: usb_reg.h update missing register description

tmedicci · Mar 14, 2023 · d699fd2 · d699fd2
1 parent a8f3205
commit d699fd2
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Showing 2 changed files with 32 additions and 26 deletions.
diff --git a/components/soc/esp32s2/include/soc/usb_reg.h b/components/soc/esp32s2/include/soc/usb_reg.h
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -1491,6 +1483,17 @@ extern "C" {
 #define USB_NZSTSOUTHSHK_M  (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S)
 #define USB_NZSTSOUTHSHK_V  0x00000001
 #define USB_NZSTSOUTHSHK_S  2
+/** USB_ENA32KHZSUSP : R/W; bitpos: [3]; default: 0;
+ *  This bit can be set only if FS PHY interface is selected.
+ *  Otherwise, this bit needs to be set to zero.
+ *  1'b0: USB 1.1 Full-Speed Serial transiver not selected
+ *  1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend
+ *  must be switched from 48 MHz to 32 KHz
+ */
+#define USB_ENA32KHZSUSP    (BIT(3))
+#define USB_ENA32KHZSUSP_M  (USB_ENA32KHZSUSP_V << USB_ENA32KHZSUSP_S)
+#define USB_ENA32KHZSUSP_V  0x00000001
+#define USB_ENA32KHZSUSP_S  3
 /** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0;
  *  Device Address.
  */

diff --git a/components/soc/esp32s3/include/soc/usb_reg.h b/components/soc/esp32s3/include/soc/usb_reg.h
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -1492,6 +1484,17 @@ extern "C" {
 #define USB_NZSTSOUTHSHK_M  (USB_NZSTSOUTHSHK_V << USB_NZSTSOUTHSHK_S)
 #define USB_NZSTSOUTHSHK_V  0x00000001
 #define USB_NZSTSOUTHSHK_S  2
+/** USB_ENA32KHZSUSP : R/W; bitpos: [3]; default: 0;
+ *  This bit can be set only if FS PHY interface is selected.
+ *  Otherwise, this bit needs to be set to zero.
+ *  1'b0: USB 1.1 Full-Speed Serial transiver not selected
+ *  1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend
+ *  must be switched from 48 MHz to 32 KHz
+ */
+#define USB_ENA32KHZSUSP    (BIT(3))
+#define USB_ENA32KHZSUSP_M  (USB_ENA32KHZSUSP_V << USB_ENA32KHZSUSP_S)
+#define USB_ENA32KHZSUSP_V  0x00000001
+#define USB_ENA32KHZSUSP_S  3
 /** USB_DEVADDR : R/W; bitpos: [11:4]; default: 0;
  *  Device Address.
  */