A Verilog code for block matrix multiplication. This project is for the Digital System Design (DSD) course.
- Mohammad Abolnejadian
- Mohammadali Khodabandelou
- Mohammadali Mohammadkhani
- Alireza Eiji
- Sina Elahimanesh
- Mohammadhossein Haji Seyyed Soleiman
- Kian Omoomi
You can syntesis this system on the FPGA using a Cad Tool. In order to do this, we recommend using ISE Xilinx. After installing the software, do the following:
- Create a new project
- Put the main module in the top level of your project
The full documentation is provided here, but it is in Persian.