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7 stars written in C++
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fastmachinelearning / hls4ml

Machine learning on FPGAs using HLS

C++ 1,235 398 Updated Sep 20, 2024

fpgasystems / fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

C++ 733 263 Updated Apr 23, 2024

kholia / xvc-esp32

Wireless JTAG 'cable' for Xilinx FPGAs. This is an 'English fork' of https://github.com/ciniml/xvc-esp32 project.

C++ 74 18 Updated Aug 26, 2021

gewuek / vitis_ai_custom_platform_flow

This project is trying to create a base vitis platform to run with DPU

C++ 48 19 Updated Jul 8, 2020

Xilinx / smartcam

C++ 25 21 Updated Mar 30, 2023

JackBonnellDevelopment / Hack_face_detect

C++ 3 Updated Oct 15, 2021

lp6m / vitis_ai_dpu_yolo

vitis_ai_dpu_yolo

C++ 1 Updated Nov 24, 2022