Passionate About RISC-V | FPGA Design & Embedded Systems Developer
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Digital-Designs-in-Verilog
Digital-Designs-in-Verilog Public"Digital-Designs-in-Verilog" is a personal project to learn various dgital designs in verilog
Verilog
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SmartIrrigation
SmartIrrigation PublicA smart irrigation system that uses IoT technology and sensors to optimize water usage in agriculture
C++
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Voting-machine-in-Verilog
Voting-machine-in-Verilog PublicThe given project counts the votes accumulated by 4 candidatses and displays them on leds
Verilog
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RISC-V-PIpeline_Core
RISC-V-PIpeline_Core PublicA pipelined RISC-V core utilizing BRAM for instruction and data memory.
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