Tags: sifive/riscv-qemu
Tags
Add gdb xml register support. This allows gdb to read misa and set breakpoints. This is a work in progress, and has a number of obvious problems, incomplete csr support, wrong int reg size for rv32, etc.
SiFive CLIC (Core Level Interrupt Controller) test-beta1
- Implements draft clic-spec (20180728)
- Implements non-vectored mode and vectored mode
- Implements mode+level+priority configuration
- Implements mode+level+priority preemption model
- Seperated M-mode (mtvec) and S-mode (stvec) delivery
- CLIC supports backwards compatible CLINT mode for
legacy interrupts using MIE/MIP,SIE/SIP (irq < 16)
depending on mtvec (MTI,MSI) and stvec (STI,SSI)
- CLINT mode supports S-mode stimecmp{h} and ssip{h}
- QEMU CLINT/CLIC Test Cases
- https://github.com/michaeljclark/qemu-riscv-tests
- Adds two experimental machines
- SiFive Freedom E-Series with CLIC
- Implements M-mode CLINT/CLIC config memory map
- Parameters
- CLICINTBITS=4
- CLICCFGMBITS=0
- CLICCFGLBITS=4
- Invocation
- qemu-system-riscv{32,64} -machine sifive_ex
- SiFive Freedom U-Series with CLIC
- Implements M-mode and S-mode CLINT/CLIC memory map
- Parameters
- CLICINTBITS=8
- CLICCFGMBITS=2
- CLICCFGLBITS=4
- Invocation
- qemu-system-riscv{32,64} -machine sifive_ux
- CLIC combined CLINT/CLIC memory map
- M-Mode CLINT = 0x02000000
- msip = 0x02000000 + hartid * 4
- mtimecmp = 0x02004000 + hartid * 4
- mtime = 0x0200bff8
- S-Mode CLINT = 0x02020000
- M-mode CLIC = 0x02080000
- clicintip = 0x02080000 + hartid * 0x1000 + 0x000
- clicintie = 0x02080000 + hartid * 0x1000 + 0x400
- clicintcfg = 0x02080000 + hartid * 0x1000 + 0x800
- cliccfg = 0x02080000 + hartid * 0x1000 + 0xc00
- S-Mode CLIC = 0x020c0000
- clicintip = 0x020c0000 + hartid * 0x1000 + 0x000
- clicintie = 0x020c0000 + hartid * 0x1000 + 0x400
- clicintcfg = 0x020c0000 + hartid * 0x1000 + 0x800
- Adds CLIC interrupt tracing (`-d trace:riscv_trap,...`)
- riscv_trap # existing core interrupt tracing
- sifive_clic_cfg # CLIC global configuration
- sifive_clic_intcfg # CLIC interrupt configuration
- sifive_clic_intie # CliC interrupt enable
- sifive_clic_intip # CLIC interrupt pending
- sifive_clic_irq # CLIC irq entry
- Notes / Limitations
- Enforces clicintcfg writes based on cliccfg and mode
- Reads/writes to intcfg/intie/intip in lower mode MMIO
apetures are currently allowed. Access checks need to
be added to suppress writes and hardwire read reults to
zero for any entries that where mode < clicintcfg.mode
- Interrupts pending bits are writable by software.
Edge/Level configuration needs to be added to control
software access to interrupt pending bits
- Selective vectoring in non-vectored mode is unimplemented
- PLIC is currently not routed via the CLIC however pending
bits can be written by software to test pre-emption.
- mnxti/snxti sets mstatus flags but returns 0 (slow path).
The CLIC state is currenetly not accessible from target/riscv
as cpu implementations can't include anything from include/hw
so the CLIC state needs to be in a CPU accessible structure.
- Potential race condition if an interrupt is posted
before the CPU has received and processed an outstanding
interrupt due to env->exccode being overwritten.
Needs changes to the interface from the CLIC so that the
CPU interrupt handler pulls the highest priority interrupt
from the CLIC at the time it is woken up. This requires the
CLIC state to be accessible from the CPU similarly to mnxti
- CPU core changes are relatively intrusive. The CPU interrupt
handling requires some abstraction/hooks for a more modular
CLIC implementation. CLIC state needs to be attached to
the CPU, and accessible to the MMIO device with hooks in
riscv_cpu_exec_interrupt and riscv_cpu_do_interrupt
Changes since v0
- Fix array index calculation in sifive_clic_realize
- Raise CLIC_LEVEL_BITS to 8 and fix assertion
- Move CLIC parameterization constants to its header
Merge branch 'qemu-for-testing' into riscv-all
Merge branch 'qemu-for-testing' into riscv-all
target/riscv/pmp: Fix address matching, granularity and debug - Rename pmp_hart_has_priv to pmp_has_access as this is a more appropriate name for tracing - Add tracing for CSR reads and writes to pmpcfg and pmpaddr using -d trace:pmpcfg_csr_read,trace:pmpcfg_csr_write, trace:pmpaddr_csr_read,trace:pmpaddr_csr_write - Add tracing for PMP access and rule matching using -d trace:pmp_has_access,trace:pmp_rule_match - Add early out if not all rules are present; short-circuit optimization bug for discontiguous rules fixed (reported by wxjstz <[email protected]>) - Fix bug where TLB entries were created for rules smaller than the page size (4096), which caused results of rules with small spans to be erroneously used in subsequent accesses - Fix integer promotion bug in pmpcfg_csr_read (also reported by wxjstz <[email protected]>) - Fix bug where PMP allowed non M-mode accesses when no rules have been configured (default behaviour is to deny access to other modes until PMP has been configured. (also reported by wxjstz <[email protected]>) - Fix illegal offsets for pmpcfg CSR accesses on rv64 (reported by wxjstz <[email protected]>) - Use size_t for PMP CSR address offsets (unsigned int can result in sign extension on some 64-bit architectures) - Add granularity parameter and mask addresss writes so that granularity can be detected. - Use NA4 bit to represent terminal granule size where G > 0 (this is implied by the specification) - Remove redundant debugging statements (unnecessar with the new tracing support). - Simplify rule matching loop and use a ternary expression that contains the entire rule match result in a similar condensed style to spike (riscv-isa-sim). Co-authored-by: wxjstz <[email protected]> Signed-off-by: Michael Clark <[email protected]>
target/riscv/pmp: Fix address matching, granularity and debug - Rename pmp_hart_has_priv to pmp_has_access as this is a more appropriate name for tracing - Add tracing for CSR reads and writes to pmpcfg and pmpaddr using -d trace:pmpcfg_csr_read,trace:pmpcfg_csr_write, trace:pmpaddr_csr_read,trace:pmpaddr_csr_write - Add tracing for PMP access and rule matching using -d trace:pmp_has_access,trace:pmp_rule_match - Add early out if not all rules are present; short-circuit optimization bug for discontiguous rules fixed (reported by wxjstz <[email protected]>) - Fix bug where TLB entries were created for rules smaller than the page size (4096), which caused results of rules with small spans to be erroneously used in subsequent accesses - Fix integer promotion bug in pmpcfg_csr_read (also reported by wxjstz <[email protected]>) - Fix bug where PMP allowed non M-mode accesses when no rules have been configured (default behaviour is to deny access to other modes until PMP has been configured. (also reported by wxjstz <[email protected]>) - Fix illegal offsets for pmpcfg CSR accesses on rv64 (reported by wxjstz <[email protected]>) - Use size_t for PMP CSR address offsets (unsigned int can result in sign extension on some 64-bit architectures) - Add granularity parameter and mask addresss writes so that granularity can be detected. - Use NA4 bit to represent terminal granule size where G > 0 (this is implied by the specification) - Remove redundant debugging statements (unnecessar with the new tracing support). - Simplify rule matching loop and use a ternary expression that contains the entire rule match result in a similar condensed style to spike (riscv-isa-sim). Co-authored-by: wxjstz <[email protected]> Signed-off-by: Michael Clark <[email protected]>
linux-uxer/riscv - fix stat on riscv32 linux-user
riscv32 linux ABI is unique in that it has a 64-bit stat
structure on 32-bit vs seperate stat and stat64 syscalls.
Test program:
#include <stdlib.h>
int
main (void)
{
int fd = open ("tmp.file", O_CREAT|O_RDWR, S_IRWXU);
if (fd == -1) {
perror ("open failed");
exit (1);
}
struct stat buf;
int result = fstat (fd, &buf);
if (result == -1) {
perror ("fstat failed");
exit (1);
}
printf ("S_ISREG (buf.st_mode) = %d\n", S_ISREG (buf.st_mode));
return 0;
}
Expected results:
$ riscv32-unknown-linux-gnu-gcc -O2 stat.c -o stat
$ qemu-riscv32 stat
S_ISREG (buf.st_mode) = 1
Signed-off-by: Michael Clark <[email protected]>
target/riscv/pmp: Handle discontiguous rules Reported-by: wxjstz <[email protected]>
Merge branch 'qemu-for-testing' into riscv-all
PreviousNext