Add scarv/xcrypto as submodule

- New submodule contains RTL from archived scarv/xcrypto-rtl repository - Point XCRYPTO_RTL environment variable at the external/xcrypto/rtl directory - Fix RTL comments about location of modules. - Fix flow scripts paths. On branch master Your branch is up-to-date with 'origin/master'. Changes to be committed: modified: .gitmodules modified: bin/conf.sh new file: external/xcrypto modified: flow/riscv-formal/rvfi-checks.cfg modified: flow/yosys/synth-cmos.tcl modified: rtl/core/frv_bitwise.v
scarv · Feb 19, 2020 · 9ecda41 · 9ecda41
1 parent b88cb2d
commit 9ecda41
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Showing 6 changed files with 36 additions and 32 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -10,3 +10,6 @@
 [submodule "external/riscv-opcodes"]
 	path = external/riscv-opcodes
 	url = https://github.com/scarv/riscv-opcodes.git
+[submodule "external/xcrypto"]
+	path = external/xcrypto
+	url = https://github.com/scarv/xcrypto.git
diff --git a/bin/conf.sh b/bin/conf.sh
@@ -11,7 +11,7 @@ if [[ -z "$VERILATOR_ROOT" ]]; then
 fi
 
 if [[ -z "$XCRYPTO_RTL" ]]; then
-    export XCRYPTO_RTL=$FRV_HOME/../../rtl
+    export XCRYPTO_RTL=$FRV_HOME/external/xcrypto/rtl
 fi
 
 export PATH=$RISCV:$PATH

diff --git a/external/xcrypto b/external/xcrypto
diff --git a/flow/riscv-formal/rvfi-checks.cfg b/flow/riscv-formal/rvfi-checks.cfg
@@ -22,21 +22,21 @@ causal    10    30
 read_verilog -sv @basedir@/../../verif/rvfi/fi_fairness.sv
 read_verilog -sv @basedir@/../../verif/rvfi/rvfi_wrapper.sv
 read_verilog -sv @basedir@/../../rtl/core/*.v
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/p_addsub/p_addsub.v
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/p_shfrot/p_shfrot.v
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_sha3/xc_sha3.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_sha256/xc_sha256.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_aessub/xc_aessub.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_aessub/xc_aessub_sbox.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_aesmix/xc_aesmix.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_malu/xc_malu.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_malu/xc_malu_divrem.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_malu/xc_malu_long.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_malu/xc_malu_mul.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_malu/xc_malu_pmul.v 
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/xc_malu/xc_malu_muldivrem.v
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/b_bop/b_bop.v
-read_verilog -sv @basedir@/../../external/xcrypto-rtl/rtl/b_lut/b_lut.v
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/p_addsub/p_addsub.v
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/p_shfrot/p_shfrot.v
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_sha3/xc_sha3.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_sha256/xc_sha256.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_aessub/xc_aessub.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_aessub/xc_aessub_sbox.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_aesmix/xc_aesmix.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_malu/xc_malu.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_malu/xc_malu_divrem.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_malu/xc_malu_long.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_malu/xc_malu_mul.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_malu/xc_malu_pmul.v 
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/xc_malu/xc_malu_muldivrem.v
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/b_bop/b_bop.v
+read_verilog -sv @basedir@/../../external/xcrypto/rtl/b_lut/b_lut.v
 
 
 
diff --git a/flow/yosys/synth-cmos.tcl b/flow/yosys/synth-cmos.tcl
@@ -3,21 +3,21 @@ yosys -import
 
 # Read in the design
 read_verilog -I$::env(FRV_HOME)/rtl/core $::env(FRV_HOME)/rtl/core/*.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/p_addsub/p_addsub.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/p_shfrot/p_shfrot.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_malu/xc_malu.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_malu/xc_malu_divrem.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_malu/xc_malu_long.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_malu/xc_malu_mul.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_malu/xc_malu_muldivrem.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_malu/xc_malu_pmul.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_sha3/xc_sha3.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_sha256/xc_sha256.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_aessub/xc_aessub.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_aessub/xc_aessub_sbox.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/xc_aesmix/xc_aesmix.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/b_bop/b_bop.v
-read_verilog $::env(FRV_HOME)/external/xcrypto-rtl/rtl/b_lut/b_lut.v
+read_verilog $::env(XCRYPTO_RTL)/p_addsub/p_addsub.v
+read_verilog $::env(XCRYPTO_RTL)/p_shfrot/p_shfrot.v
+read_verilog $::env(XCRYPTO_RTL)/xc_malu/xc_malu.v
+read_verilog $::env(XCRYPTO_RTL)/xc_malu/xc_malu_divrem.v
+read_verilog $::env(XCRYPTO_RTL)/xc_malu/xc_malu_long.v
+read_verilog $::env(XCRYPTO_RTL)/xc_malu/xc_malu_mul.v
+read_verilog $::env(XCRYPTO_RTL)/xc_malu/xc_malu_muldivrem.v
+read_verilog $::env(XCRYPTO_RTL)/xc_malu/xc_malu_pmul.v
+read_verilog $::env(XCRYPTO_RTL)/xc_sha3/xc_sha3.v
+read_verilog $::env(XCRYPTO_RTL)/xc_sha256/xc_sha256.v
+read_verilog $::env(XCRYPTO_RTL)/xc_aessub/xc_aessub.v
+read_verilog $::env(XCRYPTO_RTL)/xc_aessub/xc_aessub_sbox.v
+read_verilog $::env(XCRYPTO_RTL)/xc_aesmix/xc_aesmix.v
+read_verilog $::env(XCRYPTO_RTL)/b_bop/b_bop.v
+read_verilog $::env(XCRYPTO_RTL)/b_lut/b_lut.v
 
 # Synthesise processes ready for SCC check.
 procs

diff --git a/rtl/core/frv_bitwise.v b/rtl/core/frv_bitwise.v
@@ -79,7 +79,7 @@ wire [31:0] result_lut;
 
 generate if(XC_CLASS_BIT) begin
 
-// Lut function instance from external/xcrypto-rtl
+// Lut function instance from external/xcrypto/rtl
 b_lut i_b_lut (
 .crs1  (rs1         ), // Source register 1 (LUT input)
 .crs2  (rs2         ), // Source register 2 (LUT bottom half)