Vectored interrupts: progress save.

- mtvec fields test fails due to weird load data access errors.

- Only a problem since factoring out common timer interrupt trigger code.

- Commented out offending code calls in verif/unit/interrupts for now.

 On branch dev/ben/vectored-interrupts
 Your branch is up-to-date with 'origin/dev/ben/vectored-interrupts'.

 Changes to be committed:
	modified:   flow/gtkwave/verilator.gtkw
	modified:   rtl/core/frv_csrs.v
	modified:   rtl/core/frv_pipeline.v
	modified:   rtl/core/frv_pipeline_writeback.v
	modified:   verif/unit/Makefile.in
	modified:   verif/unit/interrupts/test_interrupts.S
	modified:   verif/unit/interrupts/test_interrupts.c

flow/gtkwave/verilator.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Tue Mar  3 09:14:33 2020
+[*] Tue Mar  3 12:38:19 2020
 [*]
-[dumpfile] "/home/ben/scarv/repos/scarv-cpu/work/riscv-compliance/rv32imc/C-ADD.vcd"
-[dumpfile_mtime] "Tue Mar  3 09:12:54 2020"
-[dumpfile_size] 1750636
+[dumpfile] "/home/ben/scarv/repos/scarv-cpu/work/unit/interrupts/interrupts.vcd"
+[dumpfile_mtime] "Tue Mar  3 12:34:10 2020"
+[dumpfile_size] 38243752
 [savefile] "/home/ben/scarv/repos/scarv-cpu/flow/gtkwave/verilator.gtkw"
-[timestart] 1
+[timestart] 91400
 [size] 1920 1025
 [pos] -1 -1
-*-9.968252 586 2626 23906 3830 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-9.297943 93495 2626 23906 3830 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] TOP.
 [treeopen] TOP.frv_core.
 [treeopen] TOP.frv_core.i_pipeline.
@@ -55,7 +55,7 @@ TOP.frv_core.rvfi_trap[0]
 TOP.frv_core.rvfi_valid[0]
 @1401200
 -RVFI
-@800200
+@c00200
 -Instruction Memory
 @28
 TOP.frv_core.imem_req
@@ -68,9 +68,9 @@ TOP.frv_core.imem_recv
 TOP.frv_core.imem_error
 @22
 TOP.frv_core.imem_rdata[31:0]
-@1000200
+@1401200
 -Instruction Memory
-@800200
+@c00200
 -Data Memory
 @28
 TOP.frv_core.i_pipeline.dmem_req
@@ -90,12 +90,12 @@ TOP.frv_core.i_pipeline.dmem_ack
 TOP.frv_core.i_pipeline.dmem_rdata[31:0]
 @28
 TOP.frv_core.i_pipeline.dmem_error
-@1000200
+@1401200
 -Data Memory
 @800200
 -Trace
 @2022
-^1 /home/ben/scarv/repos/scarv-cpu/work/unit/isw_mul/isw_mul.gtkwl
+^1 /home/ben/scarv/repos/scarv-cpu/work/unit/interrupts/interrupts.gtkwl
 TOP.frv_core.trs_instr[31:0]
 @22
 TOP.frv_core.trs_instr[31:0]
@@ -106,7 +106,7 @@ TOP.frv_core.trs_pc[31:0]
 TOP.frv_core.trs_valid
 TOP.frv_core.i_pipeline.cf_req
 TOP.frv_core.i_pipeline.cf_ack
-@22
+@23
 TOP.frv_core.i_pipeline.cf_target[31:0]
 @1000200
 -Trace
@@ -210,7 +210,7 @@ TOP.frv_core.i_pipeline.i_pipeline_s0_fetch.s1_valid
 @22
 TOP.frv_core.i_pipeline.s1_data[31:0]
 @2022
-^1 /home/ben/scarv/repos/scarv-cpu/work/unit/isw_mul/isw_mul.gtkwl
+^1 /home/ben/scarv/repos/scarv-cpu/work/unit/interrupts/interrupts.gtkwl
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.n_s2_instr[31:0]
 @28
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.s1_bubble
@@ -256,7 +256,7 @@ TOP.frv_core.i_pipeline.i_pipeline_s1_decode.i_frv_leak.leak_prng[31:0]
 TOP.frv_core.i_pipeline.s2_busy
 TOP.frv_core.i_pipeline.s2_valid
 @2022
-^1 /home/ben/scarv/repos/scarv-cpu/work/unit/isw_mul/isw_mul.gtkwl
+^3 /home/ben/scarv/repos/scarv-cpu/work/unit/isw_mul/isw_mul.gtkwl
 TOP.frv_core.i_pipeline.s2_instr[31:0]
 @c00022
 TOP.frv_core.i_pipeline.s2_opr_a[31:0]
@@ -339,7 +339,7 @@ TOP.frv_core.i_pipeline.i_pipeline_s2_execute.alu_valid
 @28
 TOP.frv_core.i_pipeline.s3_busy
 @2022
-^1 /home/ben/scarv/repos/scarv-cpu/work/unit/isw_mul/isw_mul.gtkwl
+^3 /home/ben/scarv/repos/scarv-cpu/work/unit/isw_mul/isw_mul.gtkwl
 TOP.frv_core.i_pipeline.s3_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.s3_opr_a[31:0]
@@ -453,7 +453,7 @@ TOP.frv_core.i_pipeline.i_pipeline_s4_writeback.gpr_wen
 @200
 -
 @2022
-^3 /home/ben/scarv/repos/scarv-cpu/work/unit/mtime-write/mtime-write.gtkwl
+^4 /home/ben/scarv/repos/scarv-cpu/work/unit/mtime-write/mtime-write.gtkwl
 TOP.frv_core.i_pipeline.i_pipeline_s4_writeback.trs_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.i_pipeline_s4_writeback.trs_instr[31:0]
@@ -472,24 +472,127 @@ TOP.frv_core.i_pipeline.csr_en
 TOP.frv_core.i_pipeline.csr_mepc[31:0]
 TOP.frv_core.i_pipeline.csr_mtvec[31:0]
 TOP.frv_core.i_pipeline.csr_rdata[31:0]
-@29
+@28
 TOP.frv_core.i_pipeline.csr_error
-@22
+@c00022
 TOP.frv_core.i_pipeline.csr_wdata[31:0]
 @28
+(0)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(1)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(2)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(3)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(4)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(5)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(6)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(7)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(8)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(9)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(10)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(11)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(12)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(13)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(14)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(15)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(16)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(17)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(18)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(19)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(20)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(21)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(22)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(23)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(24)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(25)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(26)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(27)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(28)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(29)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(30)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+(31)TOP.frv_core.i_pipeline.csr_wdata[31:0]
+@1401200
+-group_end
+@28
 TOP.frv_core.i_pipeline.csr_wr
 TOP.frv_core.i_pipeline.csr_wr_clr
 TOP.frv_core.i_pipeline.csr_wr_set
 @1000200
 -CSR Bus
+@800200
+-MTVEC
+@22
+TOP.frv_core.i_pipeline.i_csrs.csr_mtvec[31:0]
+@28
+TOP.frv_core.i_pipeline.i_csrs.mtvec_bad_write
+@c00022
+TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+@28
+(0)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(1)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(2)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(3)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(4)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(5)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(6)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(7)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(8)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(9)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(10)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(11)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(12)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(13)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(14)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(15)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(16)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(17)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(18)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(19)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(20)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(21)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(22)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(23)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(24)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(25)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(26)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(27)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(28)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+(29)TOP.frv_core.i_pipeline.i_csrs.n_mtvec_base[29:0]
+@1401200
+-group_end
+@24
+TOP.frv_core.i_pipeline.i_csrs.n_mtvec_mode[1:0]
+@28
+TOP.frv_core.i_pipeline.i_csrs.read_mtvec
+@22
+TOP.frv_core.i_pipeline.i_csrs.reg_mtvec[31:0]
+TOP.frv_core.i_pipeline.i_csrs.reg_mtvec_base[29:0]
+@28
+TOP.frv_core.i_pipeline.i_csrs.reg_mtvec_mode[1:0]
+TOP.frv_core.i_pipeline.i_csrs.wen_mtvec
+@200
+-
+@28
+TOP.frv_core.i_pipeline.i_pipeline_s4_writeback.cfu_trap
+TOP.frv_core.i_pipeline.i_pipeline_s4_writeback.csr_trap
+@200
+-
+@24
+TOP.frv_core.i_pipeline.i_csrs.trap_cause[5:0]
+@28
+TOP.frv_core.i_pipeline.i_csrs.trap_cpu
+TOP.frv_core.i_pipeline.i_csrs.trap_int
+@22
+TOP.frv_core.i_pipeline.i_csrs.trap_mtval[31:0]
+TOP.frv_core.i_pipeline.i_csrs.trap_pc[31:0]
+@1000200
+-MTVEC
 @22
 TOP.frv_core.i_pipeline.i_csrs.reg_mcause_cause[30:0]
 @28
 TOP.frv_core.i_pipeline.i_csrs.reg_mcause_interrupt
 @22
 TOP.frv_core.i_pipeline.i_csrs.reg_mepc[31:0]
 TOP.frv_core.i_pipeline.i_csrs.reg_mie[31:0]
-@c00200
+@800200
 -Interrupts
 @28
 TOP.frv_core.i_interrupts.g_clk
@@ -512,7 +615,7 @@ TOP.frv_core.i_interrupts.raise_mti
 TOP.frv_core.i_interrupts.sw_pending
 TOP.frv_core.i_interrupts.ti_pending
 TOP.frv_core.i_interrupts.ex_pending
-@1401200
+@1000200
 -Interrupts
 @c00200
 -Counters
@@ -550,7 +653,7 @@ TOP.frv_core.i_counters.inhibit_tm
 TOP.frv_core.i_counters.instr_ret
 @1401200
 -Counters
-@800200
+@c00200
 -GPRs
 @22
 TOP.frv_core.i_pipeline.i_gprs.gprs(0)[31:0]
@@ -585,7 +688,7 @@ TOP.frv_core.i_pipeline.i_gprs.gprs(28)[31:0]
 TOP.frv_core.i_pipeline.i_gprs.gprs(29)[31:0]
 TOP.frv_core.i_pipeline.i_gprs.gprs(30)[31:0]
 TOP.frv_core.i_pipeline.i_gprs.gprs(31)[31:0]
-@1000200
+@1401200
 -GPRs
 [pattern_trace] 1
 [pattern_trace] 0

rtl/core/frv_csrs.v

@@ -19,7 +19,8 @@ output wire [XL:0] csr_rdata        , // CSR read data
 output wire        csr_error        , // Raise invalid opcode exception.
 
 output wire [XL:0] csr_mepc         , // Current EPC.
-output wire [XL:0] csr_mtvec        , // Current MTVEC.
+output wire [XL:0] csr_mtvec        , // Current MTVEC address.
+output wire        vector_intrs     , // Vector interrupt mode (if set)
 
 input  wire        exec_mret        , // MRET instruction executed.
 
@@ -323,6 +324,7 @@ wire [31:0] reg_mtvec       = {
 };
 
 assign      csr_mtvec    = {reg_mtvec_base, 2'b00};
+assign      vector_intrs = reg_mtvec_mode[0];
 
 wire        wen_mtvec    = csr_wr && csr_addr == CSR_ADDR_MTVEC;
 

rtl/core/frv_pipeline.v

@@ -197,6 +197,7 @@ wire        csr_error  ; // Raise invalid opcode trap due to bad csr access.
 
 wire [XL:0] csr_mepc   ; // Current MEPC.
 wire [XL:0] csr_mtvec  ; // Current MTVEC.
+wire        vector_intrs;// In vectored interrupt mode.
 
 wire        exec_mret  ; // MRET instruction executed.
 
@@ -739,6 +740,7 @@ frv_pipeline_writeback #(
 .exec_mret        (exec_mret        ), // MRET instruction executed.
 .csr_mepc         (csr_mepc         ),
 .csr_mtvec        (csr_mtvec        ),
+.vector_intrs     (vector_intrs     ),
 .trs_pc           (trs_pc           ), // Trace program counter.
 .trs_instr        (trs_instr        ), // Trace instruction.
 .trs_valid        (trs_valid        ), // Trace output valid.
@@ -793,6 +795,7 @@ frv_csrs #(
 .csr_error        (csr_error        ), // Raise invalid opcode trap - bad CSR
 .csr_mepc         (csr_mepc         ), // Current MEPC.
 .csr_mtvec        (csr_mtvec        ), // Current MTVEC.
+.vector_intrs     (vector_intrs     ), // Vectored interrupt mode?
 .exec_mret        (exec_mret        ), // MRET instruction executed.
 .mstatus_mie      (mstatus_mie      ), // Global interrupt enable.
 .mie_meie         (mie_meie         ), // External interrupt enable.

rtl/core/frv_pipeline_writeback.v

@@ -92,6 +92,7 @@ output wire        exec_mret       , // MRET instruction executed.
 
 input  wire [XL:0] csr_mepc        ,
 input  wire [XL:0] csr_mtvec       ,
+input  wire        vector_intrs    , // Vector interrupt mode (if set)
 
 output wire [XL:0] trs_pc          , // Trace program counter.
 output wire [31:0] trs_instr       , // Trace instruction.
@@ -476,7 +477,7 @@ end
 assign int_trap_ack = 1'b0;
 
 // Trap occured due to CPU exception or instruction.
-assign trap_cpu   = cfu_trap || lsu_trap || s4_trap;
+assign trap_cpu   = cfu_trap || lsu_trap || s4_trap || csr_trap;
 
  // A trap occured due to interrupt. trap_cpu takes priority.
 assign trap_int   = (int_trap_req || trap_int_pending) &&
@@ -487,6 +488,7 @@ assign trap_cause = // Cause of the trap.
     lsu_b_error && lsu_store    ? TRAP_STACCESS :
     cfu_ebreak                  ? TRAP_BREAKPT  :
     cfu_ecall                   ?   TRAP_ECALLM :
+    csr_error                   ? TRAP_IOPCODE  :
     trap_int                    ? int_trap_cause:
                                   {1'b0,s4_rd}  ;
 

verif/unit/Makefile.in

@@ -8,8 +8,8 @@ UNIT_TESTS_RUN  =
 UNIT_TESTS_CLEAN=
 
 UNIT_TIMEOUT    = 20000
-UNIT_FAIL       = 0x80000084
-UNIT_PASS       = 0x8000008e
+UNIT_FAIL       = 0x80000086
+UNIT_PASS       = 0x80000090
 
 UNIT_CFLAGS     = -I$(UNIT_ROOT)/share -nostartfiles -O1
 UNIT_CFLAGS    += -march=rv32imcb_xcrypto -mabi=ilp32

verif/unit/interrupts/test_interrupts.S

@@ -66,3 +66,27 @@ timer_interrupt_handler:
     mret
 .endfunc
 
+.extern test_fail
+.extern test_pass
+
+.balign 64
+.global vector_interrupt_table
+vector_interrupt_table:
+.balign 16;  j   test_fail               // 00 - User SW interrupt / exception
+.balign 16;  j   test_fail               // 01 - Supervisor SW interrupt
+.balign 16;  j   test_fail               // 02 - Reserved
+.balign 16;  j   test_fail               // 03 - Machine SW interrupt
+.balign 16;  j   test_fail               // 04 - User Timer Interrupt
+.balign 16;  j   test_fail               // 05 - Supervisor Timer Interrupt
+.balign 16;  j   test_fail               // 06 - Reserved
+.balign 16;  j   timer_interrupt_handler // 07 - Machine Timer Interrupt
+.balign 16;  j   test_fail               // 08 - User External Interrupt
+.balign 16;  j   test_fail               // 09 - Supervisor External Interrupt
+.balign 16;  j   test_fail               // 10 - Reserved
+.balign 16;  j   test_fail               // 11 - Machine External Interrupt
+.balign 16;  j   test_fail               // 12 - Reserved
+.balign 16;  j   test_fail               // 13 - Reserved
+.balign 16;  j   test_fail               // 14 - Reserved
+.balign 16;  j   test_fail               // 15 - Reserved
+
+