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bump version to v0.9.0 due to breaking changes #113

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Oct 7, 2022
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bump version to v0.9.0 due to breaking changes #113

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bump version to v0.9.0 due to breaking changes
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@almindor
almindor committed Oct 7, 2022
commit 95cccf822f35ca602023590ab6f0063783397717
9 changes: 6 additions & 3 deletions CHANGELOG.md
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Expand Up @@ -7,13 +7,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

## [Unreleased]

## [v0.8.1] - 2022-10-06
## [v0.9.0] - 2022-10-06
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Link needs an update

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Thanks, good find. Should be ok now.


### Fixed

- Fix `asm::delay()` to ensure count register is always reloaded
- Fix reading marchid and mimpid (#107)

### Removed
- `set_msoft`, `clear_msoft`, `set_mtimer` and `clear_mtimer` removed as part of fixing issue #62

## [v0.8.0] - 2022-04-20

### Added
Expand Down Expand Up @@ -92,8 +95,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

- Fixed MSRV by restricting the upper bound of `bare-metal` version

[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.8.1...HEAD
[v0.8.1]: https://github.com/rust-embedded/riscv/compare/v0.8.1...v0.8.0
[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.9.0...HEAD
[v0.9.0]: https://github.com/rust-embedded/riscv/compare/v0.8.0...v0.9.0
[v0.8.0]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.8.0
[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.0...v0.7.0
[v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
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2 changes: 1 addition & 1 deletion Cargo.toml
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@@ -1,6 +1,6 @@
[package]
name = "riscv"
version = "0.8.1"
version = "0.9.0"
edition = "2021"
rust-version = "1.59"
repository = "https://github.com/rust-embedded/riscv"
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