Fix #9197, wrong esil for aarch64 ldr

[giuscri]

See #9197.

Test: https://github.com/radare/radare2-regressions/pull/1186

Diff is messy. Actually, the change is small.

[giuscri]

I couldn't understand this if: why having a negative offset should result in an direct ESIL translation, while for positive offset you still have to check other things - see below?

Also, resulting expression is something like dst,base,20,-,=[8] which to my understanding translates to dst = *(20-base)

What I did was moving that check right before the ESIL with the positive offset is generated, and if offset is negative change + with a -.

Indentation messed up the diff.

[radare]

Then rebase :p

…

On 20 Feb 2018, at 12:52, Giuseppe ***@***.***> wrote: @giuscri commented on this pull request. In libr/anal/p/anal_arm_cs.c: > @@ -1022,53 +1022,51 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l default: break; } - if ((int)MEMDISP64(1) < 0) { I couldn't understand this if: why having a negative offset should result in an direct ESIL translation, while for positive offset you still have to check other things - see below? Also, resulting expression is something like dst,base,20,-,=[8] which to my understanding translates to dst = *(20-base) — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or mute the thread.

[giuscri]

To make the diff cleaner? How? I'm already up to date with master

[giuscri]

Maybe I could split the change in 2, 3 commits to help diff and your review and you're squashing them while merging

[giuscri]

Actually passing -b to git diff, it ignores the change in whitespaces/indentation levels.

$ git diff upstream/master -b
diff --git a/libr/anal/p/anal_arm_cs.c b/libr/anal/p/anal_arm_cs.c
index 8bcbbc7a6..61df5545d 100644
--- a/libr/anal/p/anal_arm_cs.c
+++ b/libr/anal/p/anal_arm_cs.c
@@ -1022,10 +1022,6 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
                default:
                    break;
                }
-               if ((int)MEMDISP64(1) < 0) {
-                       r_strbuf_setf (&op->esil, "%s,%s,%"PFMT64d",-,=[%d]",
-                               REG64(0), MEMBASE64(1), -(int)MEMDISP64(1), size);
-               } else {
                if (ISMEM64(1)) {
                        if (HASMEMINDEX64(1)) {
                                if (LSHIFT2_64(1)) {
@@ -1039,6 +1035,9 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
                                if (LSHIFT2_64(1)) {
                                        r_strbuf_appendf (&op->esil, "%s,%d,%"PFMT64d",%s,+,[%d],%s,=",
                                                        MEMBASE64(1), LSHIFT2_64(1), MEMDISP64(1), DECODE_SHIFT64(1), size, REG64(0));
+                               } else if ((int)MEMDISP64(1) < 0){
+                                       r_strbuf_appendf (&op->esil, "%"PFMT64d",%s,-,DUP,tmp,=,[%d],%s,=,",
+                                                       -(int)MEMDISP64(1), MEMBASE64(1), size, REG64(0));
                                } else {
                                        r_strbuf_appendf (&op->esil, "%s,%"PFMT64d",+,DUP,tmp,=,[%d],%s,=,",
                                                        MEMBASE64(1), MEMDISP64(1), size, REG64(0));
@@ -1069,7 +1068,6 @@ static int analop64_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int l
                                        IMM64(1), size, REG64(0));
                        }
                }
-               }
                break;
                }
        case ARM64_INS_CCMP: