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A collection of ComfyUI Worflows in .json format
Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo
Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been s…
This repo is for synopsys icc2 flow for skywater 130nm PDK
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
c17 benchmark Verilog Code with Logic Encryption, RTL Synthesis, RTL to GDSII Analysis, TCL Scripting
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Generate Synthetic Benchmarks for FPGA Research
Collection of digital hardware modules & projects (benchmarks)
This is an unofficial LumaAI Dream Machine API based on Golang and Gin. It currently supports generating videos.
Implementation of ASPDAC 2021 paper: "Read your circuit: Leveraging word embedding to guide logic optimization"
Base on Synopsys platform using VCS,DC,ICC,PT.
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for thes…
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
Timing-Driven Variation-Aware Clock Mesh Synthesis Environment; programmed in Perl and TCL scripts
Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
Open Source Cell Library for Predictive CNFET Technology