fix: Update of MPFS HAL to v2.3.102

This version of MPFS HAL includes:
A fix for enabling turning on the Floating Point Unit.
A typo in one of the defines translating old interrupt naming to
the newer naming is also corrected.
Cleanup of some comments.

Jira-id: ESSBM-220

Signed-off-by: Malachy Lynch <[email protected]>

driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/mss_legacy_defines.h

@@ -470,7 +470,7 @@ extern "C" {
 #define     fabric_f2h_62_plic_IRQHandler   PLIC_f2m_62_IRQHandler
 #define     fabric_f2h_63_plic_IRQHandler   PLIC_f2m_63_IRQHandler
 
-#define     bus_error_unit_hart_0_plic_IRQHandler    PLIC_E51_bus_error_unit_hart_0_IRQHandler
+#define     bus_error_unit_hart_0_plic_IRQHandler    PLIC_E51_bus_error_unit_IRQHandler
 #define     bus_error_unit_hart_1_plic_IRQHandler    PLIC_U54_1_bus_error_unit_IRQHandler
 #define     bus_error_unit_hart_2_plic_IRQHandler    PLIC_U54_2_bus_error_unit_IRQHandler
 #define     bus_error_unit_hart_3_plic_IRQHandler    PLIC_U54_3_bus_error_unit_IRQHandler

driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/nwc/mss_ddr.c

@@ -2616,10 +2616,7 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type)
         MSSIO from reset- non default values
             Needs non default values to completely go completely OFF
             Drive bits and ibuff mode
-            Ciaran to define what need to be done
-              SAR107676
         DDR - by default put to DDR4 mode so needs active intervention
-            Bills sac spec (DDR PHY SAC spec section 6.1)
             Mode register set to 7
             Ibuff mode set to 7 (rx turned off)
             P-Code/ N-code of no relevance as not used
@@ -2629,8 +2626,6 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type)
             DDR APB ( three resets - soft reset bit 0 to 1)
                 Drive odt etc
        SGMII - from reset nothing to be done
-           See Jeff's spread sheet- default values listed
-           Extn clock off also defined in spread sheet
  */
 
 
@@ -2645,7 +2640,7 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type)
  *  IP:
  *  DECODER_DRIVER, ODT, IO all out of reset
  *
- *  DDR PHY off mode that I took from version 1.58 of the DDR SAC spec.
+ *  DDR PHY off mode procedure.
  *  1.  DDR PHY OFF mode (not used at all).
  *  1.  Set the DDR_MODE register to 7
  *  This will disable all the drive and ODT to 0, as well as set all WPU bits.
@@ -3305,10 +3300,6 @@ static uint8_t FPGA_VREFDQ_calibration_using_mtc(void)
     /*
      * To manipulate the FPGA VREF value, firmware must write to the
      * DPC_BITS register, located at physical address 0x2000 7184.
-     * Full documentation for this register can be found in
-     * DFICFG Register Map [4].
-     */
-    /*
      * See DPC_BITS definition in .h file
      */
     /* CFG_DDR_SGMII_PHY->DPC_BITS.bitfield.dpc_vrgen_h; */
@@ -3550,7 +3541,6 @@ static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC
          *  configure common memory test interface by writing registers:
          *  MT_STOP_ON_ERROR, MT_DATA_PATTERN, MT_ADDR_PATTERN, MT_ADDR_BITS
          */
-        /* see MTC user guide */
         DDRCFG->MEM_TEST.MT_STOP_ON_ERROR.MT_STOP_ON_ERROR = 0U;
         /* make sure off, will turn on later. */
         DDRCFG->MEM_TEST.MT_EN_SINGLE.MT_EN_SINGLE = 0x00U;

driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/nwc/mss_pll.c

@@ -162,8 +162,6 @@ static void mss_mux_pre_mss_pll_config(void)
      * 9:5  bclk1_sel
      * 4:0  bclk0_sel
      *
-     * From SAC spec:
-     * Table 9 1: Each gbim bank clock mux programming in MSS corner
      * The DDRPHY bank clocks bclk_horz<5:0> and bclk_vert<5:0> are driven
      * from mux's gbim<5:0> in the MSS corner. Each mux uses 5 configuration
      * bits.
@@ -291,6 +289,118 @@ __attribute__((section(".ram_codetext"))) \
     set_RTC_divisor();
 }
 
+/***************************************************************************//**
+ * mss_mux_post_mss_pll_config(void)
+ *
+ * Once the MSS is locked, the output mux is set up. This code must run from
+ * RAM, as the clock of the eNVM must be modified. The first thing changed is
+ * the eNVM clock. This will prevent L1 cache from accessing the eNVM, which it
+ * will do after the return instruction.
+ *
+ ******************************************************************************/
+__attribute__((section(".ram_codetext"))) \
+        void mss_freq_scaling(uint32_t required_freq_scaling)
+{
+   /*
+    * Modify the eNVM clock, so it now matches new MSS clock
+    *
+    * [5:0]
+    * Sets the number of AHB cycles used to generate the PNVM clock,.
+    * Clock period = (Value+1) * (1000/AHBFREQMHZ)
+    * Value must be 1 to 63 (0 defaults to 15)
+    * e.g.
+    * 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz
+    * 11 will generate a 40ns period 25MHz clock if the AHB clock is 250MHz
+    * 15 will generate a 40ns period 25MHz clock if the AHB clock is 400MHz
+    *
+    */
+    SYSREG->ENVM_CR = LIBERO_SETTING_MSS_ENVM_CR;
+
+    /* mb() makes sure clock is changed in eNVM first so its ready by the time
+    function returns. In short, it makes sure the order of processing is not
+    changed by the compiler */
+    mb();
+
+    /*
+    * The eNVM control register has a bit (ENVM_CR_CLOCK_OKAY) which may be
+    * polled to confirm the frequency has changed, prior to bumping the AHB
+    * frequency.
+    */
+    volatile uint32_t wait_for_true = 0U;
+    while ((SYSREG->ENVM_CR & ENVM_CR_CLOCK_OKAY_MASK) !=\
+            ENVM_CR_CLOCK_OKAY_MASK)
+    {
+        wait_for_true++; /* need something here to stop debugger freezing */
+    }
+
+   /*
+    * Change the MSS clock as required.
+    *
+    * CLOCK_CONFIG_CR
+    * [5:0]
+    * Sets the master synchronous clock divider
+    * bits [1:0] CPU clock divider
+    * bits [3:2] AXI clock divider
+    * bits [5:4] AHB/APB clock divider
+    * 00=/1 01=/2 10=/4 11=/8 (AHB/APB divider may not be set to /1)
+    * Reset = 0x3F
+    *
+    * SYSREG->CLOCK_CONFIG_CR = (0x0U<<0U) | (0x1U<<2U) | (0x2U<<4U);
+    * MSS clk= 80Mhz, implies CPU = 80Mhz, AXI = 40Mhz, AHB/APB = 20Mhz
+    * Until we switch in MSS PLL clock (MSS_SCB_CFM_MSS_MUX->MSSCLKMUX = 0x01)
+    * e.g. If MSS clk 800Mhz
+    * MSS clk= 800Mhz, implies CPU = 800Mhz, AXI = 400Mhz, AHB/APB = 200Mhz
+    *
+    */
+    switch(required_freq_scaling)
+    {
+        default:
+        case MSS_CLK_SCALING_NORMAL:
+            SYSREG->CLOCK_CONFIG_CR = LIBERO_SETTING_MSS_CLOCK_CONFIG_CR;
+            break;
+        case MSS_CLK_SCALING_MEDIUM:
+            SYSREG->CLOCK_CONFIG_CR = MSS_CLOCK_CONFIG_CR_MED;
+            break;
+        case MSS_CLK_SCALING_LOW:
+            SYSREG->CLOCK_CONFIG_CR = MSS_CLOCK_CONFIG_CR_LOW;
+            break;
+    }
+
+}
+
+uint32_t mss_current_pclk_freq(void)
+{
+    uint32_t pclk_freq;
+    uint32_t scale = LIBERO_SETTING_MSS_CLOCK_CONFIG_CR & (0x3UL<<4U);
+    uint32_t current_scale = SYSREG->CLOCK_CONFIG_CR & (0x3UL<<4U);
+
+    pclk_freq = LIBERO_SETTING_MSS_APB_AHB_CLK * (current_scale/scale);
+
+    return pclk_freq;
+}
+
+uint32_t mss_current_axi_freq(void)
+{
+    uint32_t axi_freq;
+    uint32_t scale = LIBERO_SETTING_MSS_CLOCK_CONFIG_CR & (0x3UL<<2U);
+    uint32_t current_scale = SYSREG->CLOCK_CONFIG_CR & (0x3UL<<2U);
+
+    axi_freq = LIBERO_SETTING_MSS_AXI_CLK * (current_scale/scale);
+
+    return axi_freq;
+}
+
+uint32_t mss_current_mss_freq(void)
+{
+    uint32_t mss_freq;
+    uint32_t scale = LIBERO_SETTING_MSS_CLOCK_CONFIG_CR & (0x3UL<<0U);
+    uint32_t current_scale = SYSREG->CLOCK_CONFIG_CR & (0x3UL<<0U);
+
+    mss_freq = LIBERO_SETTING_MSS_SYSTEM_CLK * (current_scale/scale);
+
+    return mss_freq;
+}
+
 /***************************************************************************//**
  * sgmii_mux_config(uint8_t option)
  * @param option 1 => soft reset, load RPC settings
@@ -568,7 +678,7 @@ void ddr_pll_config(REG_LOAD_METHOD option)
                                                 LIBERO_SETTING_DDR_PLL_DIV_2_3;
             CFG_DDR_SGMII_PHY->PLL_CTRL2_MAIN.PLL_CTRL2_MAIN      =\
                                                    LIBERO_SETTING_DDR_PLL_CTRL2;
-            /* Read only in RPC  todo: verify this is correct
+            /*
              * CFG_DDR_SGMII_PHY->PLL_CAL_MAIN.PLL_CAL_MAIN  =\
              *                                   LIBERO_SETTING_DDR_PLL_CAL; */
             CFG_DDR_SGMII_PHY->PLL_PHADJ_MAIN.PLL_PHADJ_MAIN      =\

driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/nwc/mss_pll.h

@@ -214,6 +214,34 @@ typedef enum REG_LOAD_METHOD_
     RPC_REG_UPDATE               = 0x01,       /*!< 1 RPC -> SCB load */
 }   REG_LOAD_METHOD;
 
+typedef enum MSS_FREQ_SCALING_OPTION_
+{
+    MSS_CLK_SCALING_NORMAL                   = 0x00,       /*!< 0 SCB clock source */
+    MSS_CLK_SCALING_MEDIUM                   = 0x01,       /*!< 1 MSS PLL clock source */
+    MSS_CLK_SCALING_LOW                      = 0x02,       /*!< 1 MSS PLL clock source */
+}   MSS_FREQ_SCALING_OPTION;
+
+#if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_LOW)
+/*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */
+#define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_LOW    0x0000003EUL
+    /* DIVIDER_CPU                       [0:2]   RW value= 0x2 */
+    /* DIVIDER_AXI                       [2:2]   RW value= 0x3 */
+    /* DIVIDER_APB_AHB                   [4:2]   RW value= 0x3 */
+#endif
+
+#if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_MED)
+/*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */
+#define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_MED    0x00000029UL
+    /* DIVIDER_CPU                       [0:2]   RW value= 0x1 */
+    /* DIVIDER_AXI                       [2:2]   RW value= 0x2 */
+    /* DIVIDER_APB_AHB                   [4:2]   RW value= 0x2 */
+#endif
+
+#define MSS_CLOCK_CONFIG_CR_LOW ((LIBERO_SETTING_MSS_CLOCK_CONFIG_CR &\
+        0xFFFFFFC0UL) | LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_LOW)
+
+#define MSS_CLOCK_CONFIG_CR_MED ((LIBERO_SETTING_MSS_CLOCK_CONFIG_CR &\
+        0xFFFFFFC0UL) | LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_MED)
 
 
 /***************************************************************************//**
@@ -351,13 +379,15 @@ void pre_configure_sgmii_and_ddr_pll_via_scb(uint8_t option);
  */
 void mss_pll_config(void);
 
-/***************************************************************************//**
-  flag_mss_pll_lock_error()
+void flag_mss_pll_lock_error(void);
 
-  Instantiate platform specific function to give error feedback on your platform
+void mss_freq_scaling(uint32_t required_freq_scaling);
 
- */
-void flag_mss_pll_lock_error(void);
+uint32_t mss_current_pclk_freq(void);
+
+uint32_t mss_current_axi_freq(void);
+
+uint32_t mss_current_mss_freq(void);
 
 #ifdef __cplusplus
 }

driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/common/nwc/mss_sgmii.c

@@ -445,7 +445,6 @@ void ddr_pvt_calibration(void)
      * Wait for IOEN from power detectors DDR and SGMII - IO enable signal from
      * System Control powers on
      *
-     * From DDR phy SAC spec:
      *      MSS processor releases dce bus to send RPC bits to IO buffer,
      *      setting each to it's programmed mode and then asserts
      *      ioen high at end of this state.

driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/mpfs_hal_version.h

@@ -18,7 +18,7 @@ extern "C" {
 
 #define MPFS_HAL_VERSION_MAJOR 2
 #define MPFS_HAL_VERSION_MINOR 3
-#define MPFS_HAL_VERSION_PATCH 100
+#define MPFS_HAL_VERSION_PATCH 102
 
 #ifdef __cplusplus
 }

driver-examples/mss/mpfs-hal/mpfs-hal-coremark/src/platform/mpfs_hal/startup_gcc/mss_utils.S

@@ -246,9 +246,9 @@ fill_cache_new_seg_address:
 turn_on_fpu:
     mv  t1,a0
     csrr t2, mhartid
-    la  t4, 1
+    li  t4, 1
     sll t4,t4,t2
-    and t4,t4,t2
+    and t4,t4,t1
     beqz t4,1f
     # enable FPU and accelerator if present, setting ignored on E51
     li t0, MSTATUS_FS | MSTATUS_XS

driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/mss_legacy_defines.h

@@ -470,7 +470,7 @@ extern "C" {
 #define     fabric_f2h_62_plic_IRQHandler   PLIC_f2m_62_IRQHandler
 #define     fabric_f2h_63_plic_IRQHandler   PLIC_f2m_63_IRQHandler
 
-#define     bus_error_unit_hart_0_plic_IRQHandler    PLIC_E51_bus_error_unit_hart_0_IRQHandler
+#define     bus_error_unit_hart_0_plic_IRQHandler    PLIC_E51_bus_error_unit_IRQHandler
 #define     bus_error_unit_hart_1_plic_IRQHandler    PLIC_U54_1_bus_error_unit_IRQHandler
 #define     bus_error_unit_hart_2_plic_IRQHandler    PLIC_U54_2_bus_error_unit_IRQHandler
 #define     bus_error_unit_hart_3_plic_IRQHandler    PLIC_U54_3_bus_error_unit_IRQHandler

driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo/src/platform/mpfs_hal/common/nwc/mss_ddr.c

@@ -2616,10 +2616,7 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type)
         MSSIO from reset- non default values
             Needs non default values to completely go completely OFF
             Drive bits and ibuff mode
-            Ciaran to define what need to be done
-              SAR107676
         DDR - by default put to DDR4 mode so needs active intervention
-            Bills sac spec (DDR PHY SAC spec section 6.1)
             Mode register set to 7
             Ibuff mode set to 7 (rx turned off)
             P-Code/ N-code of no relevance as not used
@@ -2629,8 +2626,6 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type)
             DDR APB ( three resets - soft reset bit 0 to 1)
                 Drive odt etc
        SGMII - from reset nothing to be done
-           See Jeff's spread sheet- default values listed
-           Extn clock off also defined in spread sheet
  */
 
 
@@ -2645,7 +2640,7 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type)
  *  IP:
  *  DECODER_DRIVER, ODT, IO all out of reset
  *
- *  DDR PHY off mode that I took from version 1.58 of the DDR SAC spec.
+ *  DDR PHY off mode procedure.
  *  1.  DDR PHY OFF mode (not used at all).
  *  1.  Set the DDR_MODE register to 7
  *  This will disable all the drive and ODT to 0, as well as set all WPU bits.
@@ -3305,10 +3300,6 @@ static uint8_t FPGA_VREFDQ_calibration_using_mtc(void)
     /*
      * To manipulate the FPGA VREF value, firmware must write to the
      * DPC_BITS register, located at physical address 0x2000 7184.
-     * Full documentation for this register can be found in
-     * DFICFG Register Map [4].
-     */
-    /*
      * See DPC_BITS definition in .h file
      */
     /* CFG_DDR_SGMII_PHY->DPC_BITS.bitfield.dpc_vrgen_h; */
@@ -3550,7 +3541,6 @@ static uint8_t MTC_test(uint8_t mask, uint64_t start_address, uint32_t size, MTC
          *  configure common memory test interface by writing registers:
          *  MT_STOP_ON_ERROR, MT_DATA_PATTERN, MT_ADDR_PATTERN, MT_ADDR_BITS
          */
-        /* see MTC user guide */
         DDRCFG->MEM_TEST.MT_STOP_ON_ERROR.MT_STOP_ON_ERROR = 0U;
         /* make sure off, will turn on later. */
         DDRCFG->MEM_TEST.MT_EN_SINGLE.MT_EN_SINGLE = 0x00U;