Verilator Porcelain

XMake Demo of verilator + verilog/chisel

🔥 A cross-platform build utility based on Lua

OCR software, free and offline. 开源、免费的离线OCR软件。支持截屏/批量导入图片，PDF文档识别，排除水印/页眉页脚，扫描/生成二维码。内置多国语言库。

SystemVerilog compiler and language services

Test suite designed to check compliance with the SystemVerilog standard.

Python wrapper for verilator model

website source

Tiny Tapeout 8

Demo board for TT4 and beyond

VGA Clock PMOD

📚 Community guides for open source creators

Run rocket-chip on FPGA

Modular hardware build system

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

🌈 This is the website of ChipUnion.

⚙️ This is the config of ChipUnion. It can be used to show some important information on the organization's profile. If anyone have questions, please contact us by sending email.

SystemVerilog to Verilog conversion

WAL enables programmable waveform analysis.

An open source bipedal robot control framework, based on non-linear MPC and WBC, tailered for EC-hunter80-v01 bipedal robot.

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

A library of digital diagram blocks to be used with Draw.io.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。