Code, exercises, answers, and hints to go along with the book "Functional Programming in Scala"

Open-source high-performance RISC-V processor

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

Mill is a fast JVM build tool that supports Java and Scala. 2-3x faster than Gradle and 5-10x faster than Maven for common workflows, Mill aims to make your project’s build process performant, main…

SonicBOOM: The Berkeley Out-of-Order Machine

Scala based HDL

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RISC-V SoC designed by students in UCAS

Source files for SiFive's Freedom platforms

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

chisel tutorial exercises and answers

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

A template project for beginning new Chisel work

Simple RISC-V 3-stage Pipeline in Chisel

A simple testing framework for Scala

The batteries-included testing and formal verification library for Chisel-based RTL designs.

Common RTL blocks used in SiFive's projects

A teaching-focused RISC-V CPU design used at UC Davis

A dynamic verification library for Chisel.

An exquisite superscalar RV32GC processor.

Provides dot visualizations of chisel/firrtl circuits

Yet another toy CPU.

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

Run rocket-chip on FPGA

Native Docker UI for Windows, macOS and Linux

🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.