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Merge tag 'mmc-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git…
…/ulfh/mmc
Pull MMC updates from Ulf Hansson:
"There are no updates for the MEMSTICK subsystem this time. But note
that I am also carrying a patch from the pinctrl tree, which has been
shared through an immutable branch.
Summary:
MMC core:
- Convert to reasonable timeouts for all CMD6 commands (updates for
BKOPS, CACHE_FLUSH and INAND_CMD38_ARG_EXT_CSD) for eMMC
- Respect f_max clock rate at card initialization
- Add gpiod_toggle_active_low() API
- Consolidate slot-gpio code by using gpiod_toggle_active_low()
MMC host:
- Add pinctrl_select_default_state() API
- Consolidate pintctrl code by using pinctrl_select_default_state()
- mmci: Support any block sizes for SDIO for some variants
- mmci: Enable reset control for stm32_sdmmc
- mmc_spi: Toggle SPI_CS_HIGH polarity rather than hard-coding it
- renesas_sdhi: Add support for the r8a77961 variant
- renesas_sdhi: A few minor improvements
- rockchip-dw-mshc: Add support for the rk3308 variant
- sdhci: Enable support for external DMA controllers
- sdhci: Fixup error path when sending CMD12
- sdhci-brcmstb: Add support for 7216b0 variant
- sdhci-brcmstb: Add support for command queuing (CQHCI)
- sdhci-brcmstb: Add support for eMMC HS400ES mode
- sdhci-msm: Add support for the sc7180 variant
- sdhci-msm: Add support for command queuing (CQHCI)
- sdhci-of-at91: Add support for the SAM9x60 variant
- sdhci-of-at91: Improve support for tunings
- sdhci-of-esdhc: A few fixups for some clock related issues
- sdhci-omap: Add support for the am335x and the am437x variants
- sdhci-omap: Improve support for erase operations
- sdhci-omap: Add support for external DMA"
* tag 'mmc-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (89 commits)
mmc: core: Default to generic_cmd6_time as timeout in __mmc_switch()
mmc: block: Use generic_cmd6_time when modifying INAND_CMD38_ARG_EXT_CSD
mmc: core: Specify timeouts for BKOPS and CACHE_FLUSH for eMMC
mmc: sdhci-cadence: remove unneeded 'inline' marker
dt-bindings: mmc: rockchip-dw-mshc: add description for rk3308
dt-bindings: mmc: convert rockchip dw-mshc bindings to yaml
dt-bindings: mmc: convert synopsys dw-mshc bindings to yaml
mmc: sdhci-msm: Add CQHCI support for sdhci-msm
mmc: sdhci: Let a vendor driver supply and update ADMA descriptor size
mmc: sdhci-of-esdhc: fix serious issue clock is always disabled
mmc: sdhci-of-esdhc: fix transfer mode register reading
mmc: sdhci-brcmstb: Fix incorrect switch to HS mode
mmc: sdhci-brcmstb: Add support for Command Queuing (CQE)
mmc: sdhci-brcmstb: Add shutdown callback
mmc: sdhci-brcmstb: Fix driver to defer on clk_get defer
mmc: sdhci-brcmstb: Add ability to use HS400ES transfer mode
dt-bindings: mmc: brcm,sdhci-brcmstb: Add support for 7216b0
mmc: core: limit probe clock frequency to configured f_max
mmc: sdhci-milbeaut: Remove redundant platform_get_irq error message
mmc: sdhci: fix an issue of mixing different types
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49 changes: 0 additions & 49 deletions
49
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
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125
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
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| @@ -0,0 +1,125 @@ | ||
| # SPDX-License-Identifier: GPL-2.0 | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
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| title: Rockchip designware mobile storage host controller device tree bindings | ||
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| description: | ||
| Rockchip uses the Synopsys designware mobile storage host controller | ||
| to interface a SoC with storage medium such as eMMC or SD/MMC cards. | ||
| This file documents the combined properties for the core Synopsys dw mshc | ||
| controller that are not already included in the synopsys-dw-mshc-common.yaml | ||
| file and the Rockchip specific extensions. | ||
|
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| allOf: | ||
| - $ref: "synopsys-dw-mshc-common.yaml#" | ||
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| maintainers: | ||
| - Heiko Stuebner <[email protected]> | ||
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| # Everything else is described in the common file | ||
| properties: | ||
| compatible: | ||
| oneOf: | ||
| # for Rockchip RK2928 and before RK3288 | ||
| - const: rockchip,rk2928-dw-mshc | ||
| # for Rockchip RK3288 | ||
| - const: rockchip,rk3288-dw-mshc | ||
| - items: | ||
| - enum: | ||
| # for Rockchip PX30 | ||
| - rockchip,px30-dw-mshc | ||
| # for Rockchip RK3036 | ||
| - rockchip,rk3036-dw-mshc | ||
| # for Rockchip RK322x | ||
| - rockchip,rk3228-dw-mshc | ||
| # for Rockchip RK3308 | ||
| - rockchip,rk3308-dw-mshc | ||
| # for Rockchip RK3328 | ||
| - rockchip,rk3328-dw-mshc | ||
| # for Rockchip RK3368 | ||
| - rockchip,rk3368-dw-mshc | ||
| # for Rockchip RK3399 | ||
| - rockchip,rk3399-dw-mshc | ||
| # for Rockchip RV1108 | ||
| - rockchip,rv1108-dw-mshc | ||
| - const: rockchip,rk3288-dw-mshc | ||
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| reg: | ||
| maxItems: 1 | ||
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| interrupts: | ||
| maxItems: 1 | ||
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| clocks: | ||
| minItems: 2 | ||
| maxItems: 4 | ||
| description: | ||
| Handle to "biu" and "ciu" clocks for the bus interface unit clock and | ||
| the card interface unit clock. If "ciu-drive" and "ciu-sample" are | ||
| specified in clock-names, it should also contain | ||
| handles to these clocks. | ||
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||
| clock-names: | ||
| minItems: 2 | ||
| items: | ||
| - const: biu | ||
| - const: ciu | ||
| - const: ciu-drive | ||
| - const: ciu-sample | ||
| description: | ||
| Apart from the clock-names "biu" and "ciu" two more clocks | ||
| "ciu-drive" and "ciu-sample" are supported. They are used | ||
| to control the clock phases, "ciu-sample" is required for tuning | ||
| high speed modes. | ||
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| rockchip,default-sample-phase: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| minimum: 0 | ||
| maximum: 360 | ||
| default: 0 | ||
| description: | ||
| The default phase to set "ciu-sample" at probing, | ||
| low speeds or in case where all phases work at tuning time. | ||
| If not specified 0 deg will be used. | ||
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| rockchip,desired-num-phases: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| minimum: 0 | ||
| maximum: 360 | ||
| default: 360 | ||
| description: | ||
| The desired number of times that the host execute tuning when needed. | ||
| If not specified, the host will do tuning for 360 times, | ||
| namely tuning for each degree. | ||
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| required: | ||
| - compatible | ||
| - reg | ||
| - interrupts | ||
| - clocks | ||
| - clock-names | ||
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| examples: | ||
| - | | ||
| #include <dt-bindings/clock/rk3288-cru.h> | ||
| #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| #include <dt-bindings/interrupt-controller/irq.h> | ||
| sdmmc: mmc@ff0c0000 { | ||
| compatible = "rockchip,rk3288-dw-mshc"; | ||
| reg = <0x0 0xff0c0000 0x0 0x4000>; | ||
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | ||
| clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, | ||
| <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | ||
| clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | ||
| resets = <&cru SRST_MMC0>; | ||
| reset-names = "reset"; | ||
| fifo-depth = <0x100>; | ||
| max-frequency = <150000000>; | ||
| }; | ||
| ... |
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68 changes: 68 additions & 0 deletions
68
Documentation/devicetree/bindings/mmc/synopsys-dw-mshc-common.yaml
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| # SPDX-License-Identifier: GPL-2.0 | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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| title: Synopsys Designware Mobile Storage Host Controller Common Properties | ||
|
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| allOf: | ||
| - $ref: "mmc-controller.yaml#" | ||
|
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| maintainers: | ||
| - Ulf Hansson <[email protected]> | ||
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| # Everything else is described in the common file | ||
| properties: | ||
| resets: | ||
| maxItems: 1 | ||
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| reset-names: | ||
| const: reset | ||
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| clock-frequency: | ||
| description: | ||
| Should be the frequency (in Hz) of the ciu clock. If this | ||
| is specified and the ciu clock is specified then we'll try to set the ciu | ||
| clock to this at probe time. | ||
|
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| fifo-depth: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| description: | ||
| The maximum size of the tx/rx fifo's. If this property is not | ||
| specified, the default value of the fifo size is determined from the | ||
| controller registers. | ||
|
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| card-detect-delay: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| - default: 0 | ||
| description: | ||
| Delay in milli-seconds before detecting card after card | ||
| insert event. The default value is 0. | ||
|
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| data-addr: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| description: | ||
| Override fifo address with value provided by DT. The default FIFO reg | ||
| offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) | ||
| by driver. If the controller does not follow this rule, please use | ||
| this property to set fifo address in device tree. | ||
|
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| fifo-watermark-aligned: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/flag | ||
| description: | ||
| Data done irq is expected if data length is less than | ||
| watermark in PIO mode. But fifo watermark is requested to be aligned | ||
| with data length in some SoC so that TX/RX irq can be generated with | ||
| data done irq. Add this watermark quirk to mark this requirement and | ||
| force fifo watermark setting accordingly. | ||
|
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| dmas: | ||
| maxItems: 1 | ||
|
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| dma-names: | ||
| const: rx-tx |
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