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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kern…
…el/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs. Some for SoC-family code under drivers/soc, but also some other driver updates that don't belong anywhere else. We also bring in the drivers/reset code through arm-soc. Some of the larger updates: - Qualcomm support for SMEM, SMSM, SMP2P. All used to communicate with other parts of the chip/board on these platforms, all proprietary protocols that don't fit into other subsystems and live in drivers/soc for now. - System bus driver for UniPhier - Driver for the TI Wakeup M3 IPC device - Power management for Raspberry PI + Again a bunch of other smaller updates and patches" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits) bus: uniphier: allow only built-in driver ARM: bcm2835: clarify RASPBERRYPI_FIRMWARE dependency MAINTAINERS: Drop Kumar Gala from QCOM bus: uniphier-system-bus: add UniPhier System Bus driver ARM: bcm2835: add rpi power domain driver dt-bindings: add rpi power domain driver bindings ARM: bcm2835: Define two new packets from the latest firmware. drivers/soc: make mediatek/mtk-scpsys.c explicitly non-modular soc: mediatek: SCPSYS: Add regulator support MAINTAINERS: Change QCOM entries soc: qcom: smd-rpm: Add existing platform support memory/tegra: Add number of TLB lines for Tegra124 reset: hi6220: fix modular build soc: qcom: Introduce WCNSS_CTRL SMD client ARM: qcom: select ARM_CPU_SUSPEND for power management MAINTAINERS: Add rules for Qualcomm dts files soc: qcom: enable smsm/smp2p modular build serial: msm_serial: Make config tristate soc: qcom: smp2p: Qualcomm Shared Memory Point to Point soc: qcom: smsm: Add driver for Qualcomm SMSM ...
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Documentation/devicetree/bindings/bus/uniphier-system-bus.txt
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UniPhier System Bus | ||
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The UniPhier System Bus is an external bus that connects on-board devices to | ||
the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and | ||
some control signals. It supports up to 8 banks (chip selects). | ||
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Before any access to the bus, the bus controller must be configured; the bus | ||
controller registers provide the control for the translation from the offset | ||
within each bank to the CPU-viewed address. The needed setup includes the base | ||
address, the size of each bank. Optionally, some timing parameters can be | ||
optimized for faster bus access. | ||
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Required properties: | ||
- compatible: should be "socionext,uniphier-system-bus". | ||
- reg: offset and length of the register set for the bus controller device. | ||
- #address-cells: should be 2. The first cell is the bank number (chip select). | ||
The second cell is the address offset within the bank. | ||
- #size-cells: should be 1. | ||
- ranges: should provide a proper address translation from the System Bus to | ||
the parent bus. | ||
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Note: | ||
The address region(s) that can be assigned for the System Bus is implementation | ||
defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff, | ||
while other SoCs can only use 0x40000000-0x4fffffff. There might be additional | ||
limitations depending on SoCs and the boot mode. The address translation is | ||
arbitrary as long as the banks are assigned in the supported address space with | ||
the required alignment and they do not overlap one another. | ||
For example, it is possible to map: | ||
bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff | ||
It is also possible to map: | ||
bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff | ||
There is no reason to stick to a particular translation mapping, but the | ||
"ranges" property should provide a "reasonable" default that is known to work. | ||
The software should initialize the bus controller according to it. | ||
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Example: | ||
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system-bus { | ||
compatible = "socionext,uniphier-system-bus"; | ||
reg = <0x58c00000 0x400>; | ||
#address-cells = <2>; | ||
#size-cells = <1>; | ||
ranges = <1 0x00000000 0x42000000 0x02000000 | ||
5 0x00000000 0x46000000 0x01000000>; | ||
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ethernet@1,01f00000 { | ||
compatible = "smsc,lan9115"; | ||
reg = <1 0x01f00000 0x1000>; | ||
interrupts = <0 48 4> | ||
phy-mode = "mii"; | ||
}; | ||
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uart@5,00200000 { | ||
compatible = "ns16550a"; | ||
reg = <5 0x00200000 0x20>; | ||
interrupts = <0 49 4> | ||
clock-frequency = <12288000>; | ||
}; | ||
}; | ||
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In this example, | ||
- the Ethernet device is connected at the offset 0x01f00000 of CS1 and | ||
mapped to 0x43f00000 of the parent bus. | ||
- the UART device is connected at the offset 0x00200000 of CS5 and | ||
mapped to 0x46200000 of the parent bus. |
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Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
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Hisilicon System Reset Controller | ||
====================================== | ||
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Please also refer to reset.txt in this directory for common reset | ||
controller binding usage. | ||
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The reset controller registers are part of the system-ctl block on | ||
hi6220 SoC. | ||
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Required properties: | ||
- compatible: may be "hisilicon,hi6220-sysctrl" | ||
- reg: should be register base and length as documented in the | ||
datasheet | ||
- #reset-cells: 1, see below | ||
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Example: | ||
sys_ctrl: sys_ctrl@f7030000 { | ||
compatible = "hisilicon,hi6220-sysctrl", "syscon"; | ||
reg = <0x0 0xf7030000 0x0 0x2000>; | ||
#clock-cells = <1>; | ||
#reset-cells = <1>; | ||
}; | ||
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Specifying reset lines connected to IP modules | ||
============================================== | ||
example: | ||
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uart1: serial@..... { | ||
... | ||
resets = <&sys_ctrl PERIPH_RSTEN3_UART1>; | ||
... | ||
}; | ||
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The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>. |
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Documentation/devicetree/bindings/soc/bcm/raspberrypi,bcm2835-power.txt
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Raspberry Pi power domain driver | ||
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Required properties: | ||
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- compatible: Should be "raspberrypi,bcm2835-power". | ||
- firmware: Reference to the RPi firmware device node. | ||
- #power-domain-cells: Should be <1>, we providing multiple power domains. | ||
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The valid defines for power domain are: | ||
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RPI_POWER_DOMAIN_I2C0 | ||
RPI_POWER_DOMAIN_I2C1 | ||
RPI_POWER_DOMAIN_I2C2 | ||
RPI_POWER_DOMAIN_VIDEO_SCALER | ||
RPI_POWER_DOMAIN_VPU1 | ||
RPI_POWER_DOMAIN_HDMI | ||
RPI_POWER_DOMAIN_USB | ||
RPI_POWER_DOMAIN_VEC | ||
RPI_POWER_DOMAIN_JPEG | ||
RPI_POWER_DOMAIN_H264 | ||
RPI_POWER_DOMAIN_V3D | ||
RPI_POWER_DOMAIN_ISP | ||
RPI_POWER_DOMAIN_UNICAM0 | ||
RPI_POWER_DOMAIN_UNICAM1 | ||
RPI_POWER_DOMAIN_CCP2RX | ||
RPI_POWER_DOMAIN_CSI2 | ||
RPI_POWER_DOMAIN_CPI | ||
RPI_POWER_DOMAIN_DSI0 | ||
RPI_POWER_DOMAIN_DSI1 | ||
RPI_POWER_DOMAIN_TRANSPOSER | ||
RPI_POWER_DOMAIN_CCP2TX | ||
RPI_POWER_DOMAIN_CDP | ||
RPI_POWER_DOMAIN_ARM | ||
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Example: | ||
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power: power { | ||
compatible = "raspberrypi,bcm2835-power"; | ||
firmware = <&firmware>; | ||
#power-domain-cells = <1>; | ||
}; | ||
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Example for using power domain: | ||
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&usb { | ||
power-domains = <&power RPI_POWER_DOMAIN_USB>; | ||
}; |
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Wakeup M3 IPC Driver | ||
===================== | ||
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The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor | ||
(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks | ||
that cannot be controlled from the MPU, like suspend/resume and certain deep | ||
C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver | ||
to boot the wkup_m3, it handles communication with the CM3 using IPC registers | ||
present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an | ||
API to allow the SoC PM code to execute specific PM tasks. | ||
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Wkup M3 Device Node: | ||
==================== | ||
A wkup_m3_ipc device node is used to represent the IPC registers within an | ||
SoC. | ||
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Required properties: | ||
-------------------- | ||
- compatible: Should be, | ||
"ti,am3352-wkup-m3-ipc" for AM33xx SoCs | ||
"ti,am4372-wkup-m3-ipc" for AM43xx SoCs | ||
- reg: Contains the IPC register address space to communicate | ||
with the Wakeup M3 processor | ||
- interrupts: Contains the interrupt information for the wkup_m3 | ||
interrupt that signals the MPU. | ||
- ti,rproc: phandle to the wkup_m3 rproc node so the IPC driver | ||
can boot it. | ||
- mboxes: phandles used by IPC framework to get correct mbox | ||
channel for communication. Must point to appropriate | ||
mbox_wkupm3 child node. | ||
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Example: | ||
-------- | ||
/* AM33xx */ | ||
l4_wkup: l4_wkup@44c00000 { | ||
... | ||
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scm: scm@210000 { | ||
compatible = "ti,am3-scm", "simple-bus"; | ||
reg = <0x210000 0x2000>; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
ranges = <0 0x210000 0x2000>; | ||
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... | ||
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wkup_m3_ipc: wkup_m3_ipc@1324 { | ||
compatible = "ti,am3352-wkup-m3-ipc"; | ||
reg = <0x1324 0x24>; | ||
interrupts = <78>; | ||
ti,rproc = <&wkup_m3>; | ||
mboxes = <&mailbox &mbox_wkupm3>; | ||
}; | ||
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... | ||
}; | ||
}; |
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@@ -1415,20 +1415,21 @@ W: http://www.arm.linux.org.uk/ | |
S: Maintained | ||
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ARM/QUALCOMM SUPPORT | ||
M: Kumar Gala <[email protected]> | ||
M: Andy Gross <[email protected]> | ||
M: David Brown <[email protected]> | ||
M: Andy Gross <[email protected]> | ||
M: David Brown <[email protected]> | ||
L: [email protected] | ||
L: [email protected] | ||
S: Maintained | ||
F: arch/arm/boot/dts/qcom-*.dts | ||
F: arch/arm/boot/dts/qcom-*.dtsi | ||
F: arch/arm/mach-qcom/ | ||
F: drivers/soc/qcom/ | ||
F: drivers/tty/serial/msm_serial.h | ||
F: drivers/tty/serial/msm_serial.c | ||
F: drivers/*/pm8???-* | ||
F: drivers/mfd/ssbi.c | ||
F: drivers/firmware/qcom_scm.c | ||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git | ||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git | ||
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ARM/RADISYS ENP2611 MACHINE SUPPORT | ||
M: Lennert Buytenhek <[email protected]> | ||
|
@@ -1673,6 +1674,7 @@ F: arch/arm/include/asm/hardware/cache-uniphier.h | |
F: arch/arm/mach-uniphier/ | ||
F: arch/arm/mm/cache-uniphier.c | ||
F: arch/arm64/boot/dts/socionext/ | ||
F: drivers/bus/uniphier-system-bus.c | ||
F: drivers/i2c/busses/i2c-uniphier* | ||
F: drivers/pinctrl/uniphier/ | ||
F: drivers/tty/serial/8250/8250_uniphier.c | ||
|
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