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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/lin…
…ux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "The interrupt brigade came up with the following updates: - Driver for the Marvell System Error Interrupt machinery - Overhaul of the GIC-V3 ITS driver - Small updates and fixes all over the place" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (31 commits) genirq: Fix race on spurious interrupt detection softirq: Fix typo in __do_softirq() comments genirq: Fix grammar s/an /a / irqchip/gic: Unify GIC priority definitions irqchip/gic-v3: Remove acknowledge loop dt-bindings/interrupt-controller: Add documentation for Marvell SEI controller dt-bindings/interrupt-controller: Update Marvell ICU bindings irqchip/irq-mvebu-icu: Add support for System Error Interrupts (SEI) arm64: marvell: Enable SEI driver irqchip/irq-mvebu-sei: Add new driver for Marvell SEI irqchip/irq-mvebu-icu: Support ICU subnodes irqchip/irq-mvebu-icu: Disociate ICU and NSR irqchip/irq-mvebu-icu: Clarify the reset operation of configured interrupts irqchip/irq-mvebu-icu: Fix wrong private data retrieval dt-bindings/interrupt-controller: Fix Marvell ICU length in the example genirq/msi: Allow creation of a tree-based irqdomain for platform-msi dt-bindings: irqchip: renesas-irqc: Document r8a7744 support dt-bindings: irqchip: renesas-irqc: Document R-Car E3 support irqchip/pdc: Setup all edge interrupts as rising edge at GIC irqchip/gic-v3-its: Allow use of LPI tables in reserved memory ...
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Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt
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Marvell SEI (System Error Interrupt) Controller | ||
----------------------------------------------- | ||
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Marvell SEI (System Error Interrupt) controller is an interrupt | ||
aggregator. It receives interrupts from several sources and aggregates | ||
them to a single interrupt line (an SPI) on the parent interrupt | ||
controller. | ||
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This interrupt controller can handle up to 64 SEIs, a set comes from the | ||
AP and is wired while a second set comes from the CPs by the mean of | ||
MSIs. | ||
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Required properties: | ||
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- compatible: should be one of: | ||
* "marvell,ap806-sei" | ||
- reg: SEI registers location and length. | ||
- interrupts: identifies the parent IRQ that will be triggered. | ||
- #interrupt-cells: number of cells to define an SEI wired interrupt | ||
coming from the AP, should be 1. The cell is the IRQ | ||
number. | ||
- interrupt-controller: identifies the node as an interrupt controller | ||
for AP interrupts. | ||
- msi-controller: identifies the node as an MSI controller for the CPs | ||
interrupts. | ||
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Example: | ||
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sei: interrupt-controller@3f0200 { | ||
compatible = "marvell,ap806-sei"; | ||
reg = <0x3f0200 0x40>; | ||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; | ||
#interrupt-cells = <1>; | ||
interrupt-controller; | ||
msi-controller; | ||
}; |
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