forked from analogdevicesinc/linux
-
Notifications
You must be signed in to change notification settings - Fork 3
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge branch 'remotes/lorenzo/pci/dwc'
- Add intel-gw driver for PCIe host controller on Intel Gateway SoC (Dilip Kota) - Use shared DesignWare helpers to configure Fast Training Sequence (FTS) in artpec6 (Dilip Kota) * remotes/lorenzo/pci/dwc: PCI: artpec6: Configure FTS with dwc helper function PCI: dwc: intel: PCIe RC controller driver dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
- Loading branch information
Showing
8 changed files
with
765 additions
and
7 deletions.
There are no files selected for viewing
138 changes: 138 additions & 0 deletions
138
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,138 @@ | ||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
||
title: PCIe RC controller on Intel Gateway SoCs | ||
|
||
maintainers: | ||
- Dilip Kota <[email protected]> | ||
|
||
properties: | ||
compatible: | ||
items: | ||
- const: intel,lgm-pcie | ||
- const: snps,dw-pcie | ||
|
||
device_type: | ||
const: pci | ||
|
||
"#address-cells": | ||
const: 3 | ||
|
||
"#size-cells": | ||
const: 2 | ||
|
||
reg: | ||
items: | ||
- description: Controller control and status registers. | ||
- description: PCIe configuration registers. | ||
- description: Controller application registers. | ||
|
||
reg-names: | ||
items: | ||
- const: dbi | ||
- const: config | ||
- const: app | ||
|
||
ranges: | ||
maxItems: 1 | ||
|
||
resets: | ||
maxItems: 1 | ||
|
||
clocks: | ||
maxItems: 1 | ||
|
||
phys: | ||
maxItems: 1 | ||
|
||
phy-names: | ||
const: pcie | ||
|
||
reset-gpios: | ||
maxItems: 1 | ||
|
||
linux,pci-domain: true | ||
|
||
num-lanes: | ||
maximum: 2 | ||
description: Number of lanes to use for this port. | ||
|
||
'#interrupt-cells': | ||
const: 1 | ||
|
||
interrupt-map-mask: | ||
description: Standard PCI IRQ mapping properties. | ||
|
||
interrupt-map: | ||
description: Standard PCI IRQ mapping properties. | ||
|
||
max-link-speed: | ||
description: Specify PCI Gen for link capability. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 1, 2, 3, 4 ] | ||
- default: 1 | ||
|
||
bus-range: | ||
description: Range of bus numbers associated with this controller. | ||
|
||
reset-assert-ms: | ||
description: | | ||
Delay after asserting reset to the PCIe device. | ||
maximum: 500 | ||
default: 100 | ||
|
||
required: | ||
- compatible | ||
- device_type | ||
- "#address-cells" | ||
- "#size-cells" | ||
- reg | ||
- reg-names | ||
- ranges | ||
- resets | ||
- clocks | ||
- phys | ||
- phy-names | ||
- reset-gpios | ||
- '#interrupt-cells' | ||
- interrupt-map | ||
- interrupt-map-mask | ||
|
||
additionalProperties: false | ||
|
||
examples: | ||
- | | ||
#include <dt-bindings/gpio/gpio.h> | ||
#include <dt-bindings/clock/intel,lgm-clk.h> | ||
pcie10: pcie@d0e00000 { | ||
compatible = "intel,lgm-pcie", "snps,dw-pcie"; | ||
device_type = "pci"; | ||
#address-cells = <3>; | ||
#size-cells = <2>; | ||
reg = <0xd0e00000 0x1000>, | ||
<0xd2000000 0x800000>, | ||
<0xd0a41000 0x1000>; | ||
reg-names = "dbi", "config", "app"; | ||
linux,pci-domain = <0>; | ||
max-link-speed = <4>; | ||
bus-range = <0x00 0x08>; | ||
interrupt-parent = <&ioapic1>; | ||
#interrupt-cells = <1>; | ||
interrupt-map-mask = <0 0 0 0x7>; | ||
interrupt-map = <0 0 0 1 &ioapic1 27 1>, | ||
<0 0 0 2 &ioapic1 28 1>, | ||
<0 0 0 3 &ioapic1 29 1>, | ||
<0 0 0 4 &ioapic1 30 1>; | ||
ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>; | ||
resets = <&rcu0 0x50 0>; | ||
clocks = <&cgu0 LGM_GCLK_PCIE10>; | ||
phys = <&cb0phy0>; | ||
phy-names = "pcie"; | ||
reset-assert-ms = <500>; | ||
reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; | ||
num-lanes = <2>; | ||
}; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.