Skip to content

Commit

Permalink
[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
Browse files Browse the repository at this point in the history 
    
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use.  They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
    
Signed-off-by: Atsushi Nemoto <[email protected]>
Signed-off-by: Ralf Baechle <[email protected]>
  • Loading branch information
@atsushi-nemoto @ralfbaechle
atsushi-nemoto authored and ralfbaechle committed Feb 14, 2006
1 parent 6307751 commit 41700e7
Show file tree
Hide file tree
Showing 3 changed files with 64 additions and 184 deletions.
104 changes: 14 additions & 90 deletions arch/mips/mm/c-r4k.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -471,61 +471,29 @@ struct flush_icache_range_args {
static inline void local_r4k_flush_icache_range(void *args)
{
struct flush_icache_range_args *fir_args = args;
unsigned long dc_lsize = cpu_dcache_line_size();
unsigned long ic_lsize = cpu_icache_line_size();
unsigned long sc_lsize = cpu_scache_line_size();
unsigned long start = fir_args->start;
unsigned long end = fir_args->end;
unsigned long addr, aend;

if (!cpu_has_ic_fills_f_dc) {
if (end - start > dcache_size) {
r4k_blast_dcache();
} else {
R4600_HIT_CACHEOP_WAR_IMPL;
addr = start & ~(dc_lsize - 1);
aend = (end - 1) & ~(dc_lsize - 1);

while (1) {
/* Hit_Writeback_Inv_D */
protected_writeback_dcache_line(addr);
if (addr == aend)
break;
addr += dc_lsize;
}
protected_blast_dcache_range(start, end);
}

if (!cpu_icache_snoops_remote_store) {
if (end - start > scache_size) {
if (end - start > scache_size)
r4k_blast_scache();
} else {
addr = start & ~(sc_lsize - 1);
aend = (end - 1) & ~(sc_lsize - 1);

while (1) {
/* Hit_Writeback_Inv_SD */
protected_writeback_scache_line(addr);
if (addr == aend)
break;
addr += sc_lsize;
}
}
else
protected_blast_scache_range(start, end);
}
}

if (end - start > icache_size)
r4k_blast_icache();
else {
addr = start & ~(ic_lsize - 1);
aend = (end - 1) & ~(ic_lsize - 1);
while (1) {
/* Hit_Invalidate_I */
protected_flush_icache_line(addr);
if (addr == aend)
break;
addr += ic_lsize;
}
}
else
protected_blast_icache_range(start, end);
}

static void r4k_flush_icache_range(unsigned long start, unsigned long end)
Expand Down Expand Up @@ -619,27 +587,14 @@ static void r4k_flush_icache_page(struct vm_area_struct *vma,

static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;

/* Catch bad driver code */
BUG_ON(size == 0);

if (cpu_has_subset_pcaches) {
unsigned long sc_lsize = cpu_scache_line_size();

if (size >= scache_size) {
if (size >= scache_size)
r4k_blast_scache();
return;
}

a = addr & ~(sc_lsize - 1);
end = (addr + size - 1) & ~(sc_lsize - 1);
while (1) {
flush_scache_line(a); /* Hit_Writeback_Inv_SD */
if (a == end)
break;
a += sc_lsize;
}
else
blast_scache_range(addr, addr + size);
return;
}

Expand All @@ -651,62 +606,31 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
if (size >= dcache_size) {
r4k_blast_dcache();
} else {
unsigned long dc_lsize = cpu_dcache_line_size();

R4600_HIT_CACHEOP_WAR_IMPL;
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end)
break;
a += dc_lsize;
}
blast_dcache_range(addr, addr + size);
}

bc_wback_inv(addr, size);
}

static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;

/* Catch bad driver code */
BUG_ON(size == 0);

if (cpu_has_subset_pcaches) {
unsigned long sc_lsize = cpu_scache_line_size();

if (size >= scache_size) {
if (size >= scache_size)
r4k_blast_scache();
return;
}

a = addr & ~(sc_lsize - 1);
end = (addr + size - 1) & ~(sc_lsize - 1);
while (1) {
flush_scache_line(a); /* Hit_Writeback_Inv_SD */
if (a == end)
break;
a += sc_lsize;
}
else
blast_scache_range(addr, addr + size);
return;
}

if (size >= dcache_size) {
r4k_blast_dcache();
} else {
unsigned long dc_lsize = cpu_dcache_line_size();

R4600_HIT_CACHEOP_WAR_IMPL;
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end)
break;
a += dc_lsize;
}
blast_dcache_range(addr, addr + size);
}

bc_inv(addr, size);
Expand Down
70 changes: 9 additions & 61 deletions arch/mips/mm/c-tx39.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,42 +44,25 @@ __asm__ __volatile__( \
/* TX39H-style cache flush routines. */
static void tx39h_flush_icache_all(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + icache_size);
unsigned long flags, config;

/* disable icache (set ICE#) */
local_irq_save(flags);
config = read_c0_conf();
write_c0_conf(config & ~TX39_CONF_ICE);
TX39_STOP_STREAMING();

/* invalidate icache */
while (start < end) {
cache16_unroll32(start, Index_Invalidate_I);
start += 0x200;
}

blast_icache16();
write_c0_conf(config);
local_irq_restore(flags);
}

static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
unsigned long dc_lsize = current_cpu_data.dcache.linesz;

/* Catch bad driver code */
BUG_ON(size == 0);

iob();
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
invalidate_dcache_line(a); /* Hit_Invalidate_D */
if (a == end) break;
a += dc_lsize;
}
blast_inv_dcache_range(addr, addr + size);
}


Expand Down Expand Up @@ -241,42 +224,21 @@ static void tx39_flush_data_cache_page(unsigned long addr)

static void tx39_flush_icache_range(unsigned long start, unsigned long end)
{
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
unsigned long addr, aend;

if (end - start > dcache_size)
tx39_blast_dcache();
else {
addr = start & ~(dc_lsize - 1);
aend = (end - 1) & ~(dc_lsize - 1);

while (1) {
/* Hit_Writeback_Inv_D */
protected_writeback_dcache_line(addr);
if (addr == aend)
break;
addr += dc_lsize;
}
}
else
protected_blast_dcache_range(start, end);

if (end - start > icache_size)
tx39_blast_icache();
else {
unsigned long flags, config;
addr = start & ~(dc_lsize - 1);
aend = (end - 1) & ~(dc_lsize - 1);
/* disable icache (set ICE#) */
local_irq_save(flags);
config = read_c0_conf();
write_c0_conf(config & ~TX39_CONF_ICE);
TX39_STOP_STREAMING();
while (1) {
/* Hit_Invalidate_I */
protected_flush_icache_line(addr);
if (addr == aend)
break;
addr += dc_lsize;
}
protected_blast_icache_range(start, end);
write_c0_conf(config);
local_irq_restore(flags);
}
Expand Down Expand Up @@ -311,7 +273,7 @@ static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page

static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
unsigned long end;

if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
end = addr + size;
Expand All @@ -322,20 +284,13 @@ static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
} else if (size > dcache_size) {
tx39_blast_dcache();
} else {
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end) break;
a += dc_lsize;
}
blast_dcache_range(addr, addr + size);
}
}

static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
{
unsigned long end, a;
unsigned long end;

if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
end = addr + size;
Expand All @@ -346,14 +301,7 @@ static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
} else if (size > dcache_size) {
tx39_blast_dcache();
} else {
unsigned long dc_lsize = current_cpu_data.dcache.linesz;
a = addr & ~(dc_lsize - 1);
end = (addr + size - 1) & ~(dc_lsize - 1);
while (1) {
invalidate_dcache_line(a); /* Hit_Invalidate_D */
if (a == end) break;
a += dc_lsize;
}
blast_inv_dcache_range(addr, addr + size);
}
}

Expand Down
Loading

0 comments on commit 41700e7

Please sign in to comment.