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Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturque…
…tte/linux Pull clock framework update from Michael Turquette: "The common clock framework changes for 3.10 include many fixes for existing platforms, as well as adoption of the framework by new platforms and devices. Some long-needed fixes to the core framework are here as well as new features such as improved initialization of clocks from DT as well as framework reentrancy for nested clock operations." * tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux: (44 commits) clk: add clk_ignore_unused option to keep boot clocks on clk: ux500: fix mismatched types clk: vexpress: Add separate SP810 driver clk: si5351: make clk-si5351 depend on CONFIG_OF clk: export __clk_get_flags for modular clock providers clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate. clk: sunxi: Unify oscillator clock clk: composite: allow fixed rates & fixed dividers clk: composite: rename 'div' references to 'rate' clk: add si5351 i2c common clock driver clk: add device tree fixed-factor-clock binding support clk: Properly handle notifier return values clk: ux500: abx500: Define clock tree for ab850x clk: ux500: Add support for sysctrl clocks clk: mvebu: Fix valid value range checking for cpu_freq_select clk: Fixup locking issues for clk_set_parent clk: Fixup errorhandling for clk_set_parent clk: Restructure code for __clk_reparent clk: sunxi: drop an unnecesary kmalloc clk: sunxi: drop CLK_IGNORE_UNUSED ...
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Frequently asked questions about the sunxi clock system | ||
======================================================= | ||
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This document contains useful bits of information that people tend to ask | ||
about the sunxi clock system, as well as accompanying ASCII art when adequate. | ||
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Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the | ||
system? | ||
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A: The 24MHz oscillator allows gating to save power. Indeed, if gated | ||
carelessly the system would stop functioning, but with the right | ||
steps, one can gate it and keep the system running. Consider this | ||
simplified suspend example: | ||
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While the system is operational, you would see something like | ||
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24MHz 32kHz | ||
| | ||
PLL1 | ||
\ | ||
\_ CPU Mux | ||
| | ||
[CPU] | ||
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When you are about to suspend, you switch the CPU Mux to the 32kHz | ||
oscillator: | ||
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24Mhz 32kHz | ||
| | | ||
PLL1 | | ||
/ | ||
CPU Mux _/ | ||
| | ||
[CPU] | ||
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Finally you can gate the main oscillator | ||
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32kHz | ||
| | ||
| | ||
/ | ||
CPU Mux _/ | ||
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[CPU] | ||
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Q: Were can I learn more about the sunxi clocks? | ||
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A: The linux-sunxi wiki contains a page documenting the clock registers, | ||
you can find it at | ||
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http://linux-sunxi.org/A10/CCM | ||
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The authoritative source for information at this time is the ccmu driver | ||
released by Allwinner, you can find it at | ||
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https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu |
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Binding for the axi-clkgen clock generator | ||
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This binding uses the common clock binding[1]. | ||
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
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Required properties: | ||
- compatible : shall be "adi,axi-clkgen". | ||
- #clock-cells : from common clock binding; Should always be set to 0. | ||
- reg : Address and length of the axi-clkgen register set. | ||
- clocks : Phandle and clock specifier for the parent clock. | ||
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Optional properties: | ||
- clock-output-names : From common clock binding. | ||
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Example: | ||
clock@0xff000000 { | ||
compatible = "adi,axi-clkgen"; | ||
#clock-cells = <0>; | ||
reg = <0xff000000 0x1000>; | ||
clocks = <&osc 1>; | ||
}; |
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Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
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Binding for simple fixed factor rate clock sources. | ||
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This binding uses the common clock binding[1]. | ||
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
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Required properties: | ||
- compatible : shall be "fixed-factor-clock". | ||
- #clock-cells : from common clock binding; shall be set to 0. | ||
- clock-div: fixed divider. | ||
- clock-mult: fixed multiplier. | ||
- clocks: parent clock. | ||
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Optional properties: | ||
- clock-output-names : From common clock binding. | ||
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Example: | ||
clock { | ||
compatible = "fixed-factor-clock"; | ||
clocks = <&parentclk>; | ||
#clock-cells = <0>; | ||
div = <2>; | ||
mult = <1>; | ||
}; |
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Documentation/devicetree/bindings/clock/silabs,si5351.txt
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Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. | ||
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Reference | ||
[1] Si5351A/B/C Data Sheet | ||
http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf | ||
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The Si5351a/b/c are programmable i2c clock generators with upto 8 output | ||
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only | ||
3 output clocks are accessible. The internal structure of the clock | ||
generators can be found in [1]. | ||
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==I2C device node== | ||
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Required properties: | ||
- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}". | ||
- reg: i2c device address, shall be 0x60 or 0x61. | ||
- #clock-cells: from common clock binding; shall be set to 1. | ||
- clocks: from common clock binding; list of parent clock | ||
handles, shall be xtal reference clock or xtal and clkin for | ||
si5351c only. | ||
- #address-cells: shall be set to 1. | ||
- #size-cells: shall be set to 0. | ||
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Optional properties: | ||
- silabs,pll-source: pair of (number, source) for each pll. Allows | ||
to overwrite clock source of pll A (number=0) or B (number=1). | ||
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==Child nodes== | ||
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Each of the clock outputs can be overwritten individually by | ||
using a child node to the I2C device node. If a child node for a clock | ||
output is not set, the eeprom configuration is not overwritten. | ||
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Required child node properties: | ||
- reg: number of clock output. | ||
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Optional child node properties: | ||
- silabs,clock-source: source clock of the output divider stage N, shall be | ||
0 = multisynth N | ||
1 = multisynth 0 for output clocks 0-3, else multisynth4 | ||
2 = xtal | ||
3 = clkin (si5351c only) | ||
- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. | ||
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth | ||
divider. | ||
- silabs,pll-master: boolean, multisynth can change pll frequency. | ||
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==Example== | ||
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/* 25MHz reference crystal */ | ||
ref25: ref25M { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <25000000>; | ||
}; | ||
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i2c-master-node { | ||
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/* Si5351a msop10 i2c clock generator */ | ||
si5351a: clock-generator@60 { | ||
compatible = "silabs,si5351a-msop"; | ||
reg = <0x60>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
#clock-cells = <1>; | ||
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/* connect xtal input to 25MHz reference */ | ||
clocks = <&ref25>; | ||
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/* connect xtal input as source of pll0 and pll1 */ | ||
silabs,pll-source = <0 0>, <1 0>; | ||
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/* | ||
* overwrite clkout0 configuration with: | ||
* - 8mA output drive strength | ||
* - pll0 as clock source of multisynth0 | ||
* - multisynth0 as clock source of output divider | ||
* - multisynth0 can change pll0 | ||
* - set initial clock frequency of 74.25MHz | ||
*/ | ||
clkout0 { | ||
reg = <0>; | ||
silabs,drive-strength = <8>; | ||
silabs,multisynth-source = <0>; | ||
silabs,clock-source = <0>; | ||
silabs,pll-master; | ||
clock-frequency = <74250000>; | ||
}; | ||
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/* | ||
* overwrite clkout1 configuration with: | ||
* - 4mA output drive strength | ||
* - pll1 as clock source of multisynth1 | ||
* - multisynth1 as clock source of output divider | ||
* - multisynth1 can change pll1 | ||
*/ | ||
clkout1 { | ||
reg = <1>; | ||
silabs,drive-strength = <4>; | ||
silabs,multisynth-source = <1>; | ||
silabs,clock-source = <0>; | ||
pll-master; | ||
}; | ||
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/* | ||
* overwrite clkout2 configuration with: | ||
* - xtal as clock source of output divider | ||
*/ | ||
clkout2 { | ||
reg = <2>; | ||
silabs,clock-source = <2>; | ||
}; | ||
}; | ||
}; |
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Device Tree Clock bindings for arch-sunxi | ||
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This binding uses the common clock binding[1]. | ||
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
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Required properties: | ||
- compatible : shall be one of the following: | ||
"allwinner,sun4i-osc-clk" - for a gatable oscillator | ||
"allwinner,sun4i-pll1-clk" - for the main PLL clock | ||
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock | ||
"allwinner,sun4i-axi-clk" - for the AXI clock | ||
"allwinner,sun4i-axi-gates-clk" - for the AXI gates | ||
"allwinner,sun4i-ahb-clk" - for the AHB clock | ||
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates | ||
"allwinner,sun4i-apb0-clk" - for the APB0 clock | ||
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates | ||
"allwinner,sun4i-apb1-clk" - for the APB1 clock | ||
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing | ||
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates | ||
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Required properties for all clocks: | ||
- reg : shall be the control register address for the clock. | ||
- clocks : shall be the input parent clock(s) phandle for the clock | ||
- #clock-cells : from common clock binding; shall be set to 0 except for | ||
"allwinner,sun4i-*-gates-clk" where it shall be set to 1 | ||
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Additionally, "allwinner,sun4i-*-gates-clk" clocks require: | ||
- clock-output-names : the corresponding gate names that the clock controls | ||
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For example: | ||
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osc24M: osc24M@01c20050 { | ||
#clock-cells = <0>; | ||
compatible = "allwinner,sun4i-osc-clk"; | ||
reg = <0x01c20050 0x4>; | ||
clocks = <&osc24M_fixed>; | ||
}; | ||
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pll1: pll1@01c20000 { | ||
#clock-cells = <0>; | ||
compatible = "allwinner,sun4i-pll1-clk"; | ||
reg = <0x01c20000 0x4>; | ||
clocks = <&osc24M>; | ||
}; | ||
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cpu: cpu@01c20054 { | ||
#clock-cells = <0>; | ||
compatible = "allwinner,sun4i-cpu-clk"; | ||
reg = <0x01c20054 0x4>; | ||
clocks = <&osc32k>, <&osc24M>, <&pll1>; | ||
}; | ||
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Gate clock outputs | ||
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The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs; | ||
their corresponding offsets as present on sun4i are listed below. Note that | ||
some of these gates are not present on sun5i. | ||
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* AXI gates ("allwinner,sun4i-axi-gates-clk") | ||
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DRAM 0 | ||
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* AHB gates ("allwinner,sun4i-ahb-gates-clk") | ||
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USB0 0 | ||
EHCI0 1 | ||
OHCI0 2* | ||
EHCI1 3 | ||
OHCI1 4* | ||
SS 5 | ||
DMA 6 | ||
BIST 7 | ||
MMC0 8 | ||
MMC1 9 | ||
MMC2 10 | ||
MMC3 11 | ||
MS 12** | ||
NAND 13 | ||
SDRAM 14 | ||
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ACE 16 | ||
EMAC 17 | ||
TS 18 | ||
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SPI0 20 | ||
SPI1 21 | ||
SPI2 22 | ||
SPI3 23 | ||
PATA 24 | ||
SATA 25** | ||
GPS 26* | ||
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VE 32 | ||
TVD 33 | ||
TVE0 34 | ||
TVE1 35 | ||
LCD0 36 | ||
LCD1 37 | ||
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CSI0 40 | ||
CSI1 41 | ||
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HDMI 43 | ||
DE_BE0 44 | ||
DE_BE1 45 | ||
DE_FE0 46 | ||
DE_FE1 47 | ||
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MP 50 | ||
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MALI400 52 | ||
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* APB0 gates ("allwinner,sun4i-apb0-gates-clk") | ||
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CODEC 0 | ||
SPDIF 1* | ||
AC97 2 | ||
IIS 3 | ||
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PIO 5 | ||
IR0 6 | ||
IR1 7 | ||
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KEYPAD 10 | ||
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* APB1 gates ("allwinner,sun4i-apb1-gates-clk") | ||
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I2C0 0 | ||
I2C1 1 | ||
I2C2 2 | ||
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CAN 4 | ||
SCR 5 | ||
PS20 6 | ||
PS21 7 | ||
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UART0 16 | ||
UART1 17 | ||
UART2 18 | ||
UART3 19 | ||
UART4 20 | ||
UART5 21 | ||
UART6 22 | ||
UART7 23 | ||
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Notation: | ||
[*]: The datasheet didn't mention these, but they are present on AW code | ||
[**]: The datasheet had this marked as "NC" but they are used on AW code |
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