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Enable devices to signal interrupts via PCI memory cycles. rev6: * fix enable/disable typo, Michael Ellerman rev5: * fix up ack, enable, and disable for iop13xx_msi_chip rev4: * move smp compile fix to separate patch * use dynamic_irq_init in create_irq() * hookup mask/unmask routines in iop13xx_msi_chip rev3: * change msi.c to use linux/smp.h instead of asm/smp.h * call dynamic_irq_cleanup at destroy_irq time rev2: * destroy_irq did not take the full 128 bits of msi_irq_in_use into account * added missing '&' for calls to test_and_set_bit and clear_bit [[email protected]: review comments/suggestions] [[email protected]: cleanups/forward port to 2.6-git] Signed-off-by: Daniel Wolstenholme <[email protected]> Signed-off-by: Dan Williams <[email protected]> Acked-by: Eric W. Biederman <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Russell King <[email protected]>
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Daniel Wolstenholme
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Russell King
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May 11, 2007
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/* | ||
* arch/arm/mach-iop13xx/msi.c | ||
* | ||
* PCI MSI support for the iop13xx processor | ||
* | ||
* Copyright (c) 2006, Intel Corporation. | ||
* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms and conditions of the GNU General Public License, | ||
* version 2, as published by the Free Software Foundation. | ||
* | ||
* This program is distributed in the hope it will be useful, but WITHOUT | ||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
* more details. | ||
* | ||
* You should have received a copy of the GNU General Public License along with | ||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple | ||
* Place - Suite 330, Boston, MA 02111-1307 USA. | ||
* | ||
*/ | ||
#include <linux/pci.h> | ||
#include <linux/msi.h> | ||
#include <asm/mach/irq.h> | ||
#include <asm/irq.h> | ||
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#define IOP13XX_NUM_MSI_IRQS 128 | ||
static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); | ||
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/* IMIPR0 CP6 R8 Page 1 | ||
*/ | ||
static inline u32 read_imipr_0(void) | ||
{ | ||
u32 val; | ||
asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); | ||
return val; | ||
} | ||
static inline void write_imipr_0(u32 val) | ||
{ | ||
asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); | ||
} | ||
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/* IMIPR1 CP6 R9 Page 1 | ||
*/ | ||
static inline u32 read_imipr_1(void) | ||
{ | ||
u32 val; | ||
asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); | ||
return val; | ||
} | ||
static inline void write_imipr_1(u32 val) | ||
{ | ||
asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); | ||
} | ||
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/* IMIPR2 CP6 R10 Page 1 | ||
*/ | ||
static inline u32 read_imipr_2(void) | ||
{ | ||
u32 val; | ||
asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); | ||
return val; | ||
} | ||
static inline void write_imipr_2(u32 val) | ||
{ | ||
asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); | ||
} | ||
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/* IMIPR3 CP6 R11 Page 1 | ||
*/ | ||
static inline u32 read_imipr_3(void) | ||
{ | ||
u32 val; | ||
asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); | ||
return val; | ||
} | ||
static inline void write_imipr_3(u32 val) | ||
{ | ||
asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); | ||
} | ||
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static u32 (*read_imipr[])(void) = { | ||
read_imipr_0, | ||
read_imipr_1, | ||
read_imipr_2, | ||
read_imipr_3, | ||
}; | ||
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static void (*write_imipr[])(u32) = { | ||
write_imipr_0, | ||
write_imipr_1, | ||
write_imipr_2, | ||
write_imipr_3, | ||
}; | ||
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static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) | ||
{ | ||
int i, j; | ||
unsigned long status; | ||
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/* read IMIPR registers and find any active interrupts, | ||
* then call ISR for each active interrupt | ||
*/ | ||
for (i = 0; i < ARRAY_SIZE(read_imipr); i++) { | ||
status = (read_imipr[i])(); | ||
if (!status) | ||
continue; | ||
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do { | ||
j = find_first_bit(&status, 32); | ||
(write_imipr[i])(1 << j); /* write back to clear bit */ | ||
desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i); | ||
desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc); | ||
status = (read_imipr[i])(); | ||
} while (status); | ||
} | ||
} | ||
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void __init iop13xx_msi_init(void) | ||
{ | ||
set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); | ||
} | ||
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/* | ||
* Dynamic irq allocate and deallocation | ||
*/ | ||
int create_irq(void) | ||
{ | ||
int irq, pos; | ||
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again: | ||
pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS); | ||
irq = IRQ_IOP13XX_MSI_0 + pos; | ||
if (irq > NR_IRQS) | ||
return -ENOSPC; | ||
/* test_and_set_bit operates on 32-bits at a time */ | ||
if (test_and_set_bit(pos, msi_irq_in_use)) | ||
goto again; | ||
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dynamic_irq_init(irq); | ||
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return irq; | ||
} | ||
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void destroy_irq(unsigned int irq) | ||
{ | ||
int pos = irq - IRQ_IOP13XX_MSI_0; | ||
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dynamic_irq_cleanup(irq); | ||
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clear_bit(pos, msi_irq_in_use); | ||
} | ||
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void arch_teardown_msi_irq(unsigned int irq) | ||
{ | ||
destroy_irq(irq); | ||
} | ||
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static void iop13xx_msi_nop(unsigned int irq) | ||
{ | ||
return; | ||
} | ||
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static struct irq_chip iop13xx_msi_chip = { | ||
.name = "PCI-MSI", | ||
.ack = iop13xx_msi_nop, | ||
.enable = unmask_msi_irq, | ||
.disable = mask_msi_irq, | ||
.mask = mask_msi_irq, | ||
.unmask = unmask_msi_irq, | ||
}; | ||
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int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | ||
{ | ||
int id, irq = create_irq(); | ||
struct msi_msg msg; | ||
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if (irq < 0) | ||
return irq; | ||
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set_irq_msi(irq, desc); | ||
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msg.address_hi = 0x0; | ||
msg.address_lo = IOP13XX_MU_MIMR_PCI; | ||
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id = iop13xx_cpu_id(); | ||
msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); | ||
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write_msi_msg(irq, &msg); | ||
set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); | ||
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return irq; | ||
} |
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Original file line number | Diff line number | Diff line change |
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#ifndef _IOP13XX_MSI_H_ | ||
#define _IOP13XX_MSI_H_ | ||
#ifdef CONFIG_PCI_MSI | ||
void iop13xx_msi_init(void); | ||
#else | ||
static inline void iop13xx_msi_init(void) | ||
{ | ||
return; | ||
} | ||
#endif | ||
#endif |