spi: spi-nor: fix macro/structures alignments

Use the same alignements as are used by other code. No functional changes. Signed-off-by: Michal Simek <[email protected]>
mrcsosa · Jan 31, 2022 · 2f46ff8 · 2f46ff8
1 parent 1253e54
commit 2f46ff8
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Showing 3 changed files with 13 additions and 13 deletions.
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
@@ -383,7 +383,7 @@ struct flash_info {
 					 * protection bits. Usually these will
 					 * power-up in a write-protected state.
 					 */
-#define	SST_GLOBAL_PROT_UNLK	BIT(24)	/* Unlock the Global protection for
+#define SST_GLOBAL_PROT_UNLK	BIT(24)	/* Unlock the Global protection for
 					 * sst flashes
 					 */
 #define SPI_NOR_BP3_SR_BIT5	BIT(25) /*

diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
@@ -206,14 +206,14 @@ static struct flash_info issi_parts[] = {
 			SECT_4K | SPI_NOR_DUAL_READ |
 			SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
 			SPI_NOR_4B_OPCODES) },
-        { "is25lp01g", INFO(0x9d601b, 0, 64 * 1024, 2048,
-                        SECT_4K | SPI_NOR_DUAL_READ |
-                        SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
-                        SPI_NOR_4B_OPCODES) },
-        { "is25wp01g", INFO(0x9d701b, 0, 64 * 1024, 2048,
-                        SECT_4K | SPI_NOR_DUAL_READ |
-                        SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
-                        SPI_NOR_4B_OPCODES) },
+	{ "is25lp01g", INFO(0x9d601b, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ |
+			SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
+			SPI_NOR_4B_OPCODES) },
+	{ "is25wp01g", INFO(0x9d701b, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ |
+			SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
+			SPI_NOR_4B_OPCODES) },
 	{ "is25wx256",  INFO(0x9d5b19, 0, 128 * 1024, 256,
 			     SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
 			     SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ |

diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
@@ -103,7 +103,7 @@
 
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR		0x17	/* Bank register write */
-#define	SPINOR_OP_BRRD		0x16	/* Bank register read */
+#define SPINOR_OP_BRRD		0x16	/* Bank register read */
 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
 
 /* Used for Micron flashes only. */
@@ -122,9 +122,9 @@
 #define SR_BP0			BIT(2)	/* Block protect 0 */
 #define SR_BP1			BIT(3)	/* Block protect 1 */
 #define SR_BP2			BIT(4)	/* Block protect 2 */
-#define	SR_BP_BIT_OFFSET	2	/* Offset to Block protect 0 */
-#define	SR_BP_BIT_MASK		(SR_BP2 | SR_BP1 | SR_BP0)
-#define SR_BP3                 BIT(6)  /* Block protect 3 */
+#define SR_BP_BIT_OFFSET	2	/* Offset to Block protect 0 */
+#define SR_BP_BIT_MASK		(SR_BP2 | SR_BP1 | SR_BP0)
+#define SR_BP3			BIT(6)	/* Block protect 3 */
 #define SR_TB_BIT5		BIT(5)	/* Top/Bottom protect */
 #define SR_BP3_BIT6		BIT(6)	/* Block protect 3 */
 #define SR_BP3_BIT5		BIT(5)	/* Block protect 3 */