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Merge tag 'usb-4.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/…
…git/gregkh/usb Pull USB updates from Greg KH: "Here is the big USB drivers update for 4.5-rc1. Lots of gadget driver updates and fixes, like usual, and a mix of other USB driver updates as well. Full details in the shortlog. All of these have been in linux-next for a while" * tag 'usb-4.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (191 commits) MAINTAINERS: change my email address USB: usbmon: remove assignment from IS_ERR argument USB: mxu11x0: drop redundant function name from error messages USB: mxu11x0: fix debug-message typos USB: mxu11x0: rename usb-serial driver USB: mxu11x0: fix modem-control handling on B0-transitions USB: mxu11x0: fix memory leak on firmware download USB: mxu11x0: fix memory leak in port-probe error path USB: serial: add Moxa UPORT 11x0 driver USB: cp210x: add ID for ELV Marble Sound Board 1 usb: chipidea: otg: use usb autosuspend to suspend bus for HNP usb: chipidea: host: set host to be null after hcd is freed usb: chipidea: removing of_find_property usb: chipidea: implement platform shutdown callback usb: chipidea: clean up CONFIG_USB_CHIPIDEA_DEBUG reference usb: chipidea: delete static debug support usb: chipidea: support debugfs without CONFIG_USB_CHIPIDEA_DEBUG usb: chipidea: udc: improve error handling on _hardware_enqueue usb: chipidea: udc: _ep_queue and _hw_queue cleanup usb: dwc3: of-simple: fix build warning on !PM ...
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@@ -134,19 +134,21 @@ Description: | |
enabled for the device. Developer can write y/Y/1 or n/N/0 to | ||
the file to enable/disable the feature. | ||
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What: /sys/bus/usb/devices/.../power/usb3_hardware_lpm | ||
Date: June 2015 | ||
What: /sys/bus/usb/devices/.../power/usb3_hardware_lpm_u1 | ||
/sys/bus/usb/devices/.../power/usb3_hardware_lpm_u2 | ||
Date: November 2015 | ||
Contact: Kevin Strasser <[email protected]> | ||
Lu Baolu <[email protected]> | ||
Description: | ||
If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged | ||
in to a xHCI host which supports link PM, it will check if U1 | ||
and U2 exit latencies have been set in the BOS descriptor; if | ||
the check is is passed and the host supports USB3 hardware LPM, | ||
the check is passed and the host supports USB3 hardware LPM, | ||
USB3 hardware LPM will be enabled for the device and the USB | ||
device directory will contain a file named | ||
power/usb3_hardware_lpm. The file holds a string value (enable | ||
or disable) indicating whether or not USB3 hardware LPM is | ||
enabled for the device. | ||
device directory will contain two files named | ||
power/usb3_hardware_lpm_u1 and power/usb3_hardware_lpm_u2. These | ||
files hold a string value (enable or disable) indicating whether | ||
or not USB3 hardware LPM U1 or U2 is enabled for the device. | ||
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What: /sys/bus/usb/devices/.../removable | ||
Date: February 2012 | ||
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@@ -187,6 +189,17 @@ Description: | |
The file will read "hotplug", "wired" and "not used" if the | ||
information is available, and "unknown" otherwise. | ||
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What: /sys/bus/usb/devices/.../(hub interface)/portX/usb3_lpm_permit | ||
Date: November 2015 | ||
Contact: Lu Baolu <[email protected]> | ||
Description: | ||
Some USB3.0 devices are not friendly to USB3 LPM. usb3_lpm_permit | ||
attribute allows enabling/disabling usb3 lpm of a port. It takes | ||
effect both before and after a usb device is enumerated. Supported | ||
values are "0" if both u1 and u2 are NOT permitted, "u1" if only u1 | ||
is permitted, "u2" if only u2 is permitted, "u1_u2" if both u1 and | ||
u2 are permitted. | ||
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What: /sys/bus/usb/devices/.../power/usb2_lpm_l1_timeout | ||
Date: May 2013 | ||
Contact: Mathias Nyman <[email protected]> | ||
|
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Hisilicon hi6220 usb PHY | ||
----------------------- | ||
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Required properties: | ||
- compatible: should be "hisilicon,hi6220-usb-phy" | ||
- #phy-cells: must be 0 | ||
- hisilicon,peripheral-syscon: phandle of syscon used to control phy. | ||
Refer to phy/phy-bindings.txt for the generic PHY binding properties | ||
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Example: | ||
usb_phy: usbphy { | ||
compatible = "hisilicon,hi6220-usb-phy"; | ||
#phy-cells = <0>; | ||
phy-supply = <&fixed_5v_hub>; | ||
hisilicon,peripheral-syscon = <&sys_ctrl>; | ||
}; |
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Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
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* Renesas R-Car generation 3 USB 2.0 PHY | ||
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This file provides information on what the device node for the R-Car generation | ||
3 USB 2.0 PHY contains. | ||
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Required properties: | ||
- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795 | ||
SoC. | ||
- reg: offset and length of the partial USB 2.0 Host register block. | ||
- reg-names: must be "usb2_host". | ||
- clocks: clock phandle and specifier pair(s). | ||
- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. | ||
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Optional properties: | ||
To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are | ||
combined, the device tree node should set HSUSB properties to reg and reg-names | ||
properties. This is because HSUSB has registers to select USB 2.0 host or | ||
peripheral at that channel: | ||
- reg: offset and length of the partial HSUSB register block. | ||
- reg-names: must be "hsusb". | ||
- interrupts: interrupt specifier for the PHY. | ||
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Example (R-Car H3): | ||
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usb-phy@ee080200 { | ||
compatible = "renesas,usb2-phy-r8a7795"; | ||
reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>; | ||
reg-names = "usb2_host", "hsusb"; | ||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>, | ||
<&mstp7_clks R8A7795_CLK_HSUSB>; | ||
}; | ||
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usb-phy@ee0a0200 { | ||
compatible = "renesas,usb2-phy-r8a7795"; | ||
reg = <0 0xee0a0200 0 0x700>; | ||
reg-names = "usb2_host"; | ||
clocks = <&mstp7_clks R8A7795_CLK_EHCI0>; | ||
}; |
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Xilinx SuperSpeed DWC3 USB SoC controller | ||
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Required properties: | ||
- compatible: Should contain "xlnx,zynqmp-dwc3" | ||
- clocks: A list of phandles for the clocks listed in clock-names | ||
- clock-names: Should contain the following: | ||
"bus_clk" Master/Core clock, have to be >= 125 MHz for SS | ||
operation and >= 60MHz for HS operation | ||
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"ref_clk" Clock source to core during PHY power down | ||
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Required child node: | ||
A child node must exist to represent the core DWC3 IP block. The name of | ||
the node is not important. The content of the node is defined in dwc3.txt. | ||
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Example device node: | ||
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usb@0 { | ||
#address-cells = <0x2>; | ||
#size-cells = <0x1>; | ||
status = "okay"; | ||
compatible = "xlnx,zynqmp-dwc3"; | ||
clock-names = "bus_clk" "ref_clk"; | ||
clocks = <&clk125>, <&clk125>; | ||
ranges; | ||
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dwc3@fe200000 { | ||
compatible = "snps,dwc3"; | ||
reg = <0x0 0xfe200000 0x40000>; | ||
interrupts = <0x0 0x41 0x4>; | ||
dr_mode = "host"; | ||
}; | ||
}; |
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MT8173 xHCI | ||
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The device node for Mediatek SOC USB3.0 host controller | ||
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Required properties: | ||
- compatible : should contain "mediatek,mt8173-xhci" | ||
- reg : specifies physical base address and size of the registers, | ||
the first one for MAC, the second for IPPC | ||
- interrupts : interrupt used by the controller | ||
- power-domains : a phandle to USB power domain node to control USB's | ||
mtcmos | ||
- vusb33-supply : regulator of USB avdd3.3v | ||
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- clocks : a list of phandle + clock-specifier pairs, one for each | ||
entry in clock-names | ||
- clock-names : must contain | ||
"sys_ck": for clock of xHCI MAC | ||
"wakeup_deb_p0": for USB wakeup debounce clock of port0 | ||
"wakeup_deb_p1": for USB wakeup debounce clock of port1 | ||
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- phys : a list of phandle + phy specifier pairs | ||
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Optional properties: | ||
- mediatek,wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup | ||
mode; | ||
- mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup | ||
control register, it depends on "mediatek,wakeup-src". | ||
- vbus-supply : reference to the VBUS regulator; | ||
- usb3-lpm-capable : supports USB3.0 LPM | ||
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Example: | ||
usb30: usb@11270000 { | ||
compatible = "mediatek,mt8173-xhci"; | ||
reg = <0 0x11270000 0 0x1000>, | ||
<0 0x11280700 0 0x0100>; | ||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; | ||
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; | ||
clocks = <&topckgen CLK_TOP_USB30_SEL>, | ||
<&pericfg CLK_PERI_USB0>, | ||
<&pericfg CLK_PERI_USB1>; | ||
clock-names = "sys_ck", | ||
"wakeup_deb_p0", | ||
"wakeup_deb_p1"; | ||
phys = <&phy_port0 PHY_TYPE_USB3>, | ||
<&phy_port1 PHY_TYPE_USB2>; | ||
vusb33-supply = <&mt6397_vusb_reg>; | ||
vbus-supply = <&usb_p1_vbus>; | ||
usb3-lpm-capable; | ||
mediatek,syscon-wakeup = <&pericfg>; | ||
mediatek,wakeup-src = <1>; | ||
}; |
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Renesas Electronics USB3.0 Peripheral driver | ||
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Required properties: | ||
- compatible: Must contain one of the following: | ||
- "renesas,r8a7795-usb3-peri" | ||
- reg: Base address and length of the register for the USB3.0 Peripheral | ||
- interrupts: Interrupt specifier for the USB3.0 Peripheral | ||
- clocks: clock phandle and specifier pair | ||
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Example: | ||
usb3_peri0: usb@ee020000 { | ||
compatible = "renesas,r8a7795-usb3-peri"; | ||
reg = <0 0xee020000 0 0x400>; | ||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&cpg CPG_MOD 328>; | ||
}; | ||
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usb3_peri1: usb@ee060000 { | ||
compatible = "renesas,r8a7795-usb3-peri"; | ||
reg = <0 0xee060000 0 0x400>; | ||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&cpg CPG_MOD 327>; | ||
}; |
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