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Merge tag 'soc-drivers-6.11' of git://git.kernel.org/pub/scm/linux/ke…
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…rnel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
 "The updates to the mediatek, allwinner, ti, tegra, microchip, stm32,
  samsung, imx, zynq and amlogic platoforms are fairly small maintenance
  changes, either addressing minor mistakes or enabling additional
  hardware.

  The qualcomm platform changes add a number of features and are larger
  than the other ones combined, introducing the use of linux/cleanup.h
  across several drivers, adding support for Snapdragon X1E and other
  SoCs in platform drivers, a new "protection domain mapper" driver, and
  a "shared memory bridge" driver.

  The cznic "turris omnia" router based on Marvell Armada gets a
  platform driver that talks to the board specific microcontroller.

  The reset and cache subsystems get a few minor updates to SoC specific
  drivers, while the ff-a, scmi and optee firmware drivers get some code
  refactoring and new features"

* tag 'soc-drivers-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (122 commits)
  firmware: turris-mox-rwtm: Initialize completion before mailbox
  firmware: turris-mox-rwtm: Fix checking return value of wait_for_completion_timeout()
  firmware: turris-mox-rwtm: Do not complete if there are no waiters
  MAINTAINERS: drop riscv list from cache controllers
  platform: cznic: turris-omnia-mcu: fix Kconfig dependencies
  bus: sunxi-rsb: Constify struct regmap_bus
  soc: sunxi: sram: Constify struct regmap_config
  platform: cznic: turris-omnia-mcu: Depend on WATCHDOG
  platform: cznic: turris-omnia-mcu: Depend on OF
  soc: samsung: exynos-pmu: add support for PMU_ALIVE non atomic registers
  arm64: stm32: enable scmi regulator for stm32
  firmware: qcom: tzmem: blacklist more platforms for SHM Bridge
  soc: qcom: wcnss: simplify with cleanup.h
  soc: qcom: pdr: simplify with cleanup.h
  soc: qcom: ocmem: simplify with cleanup.h
  soc: qcom: mdt_loader: simplify with cleanup.h
  soc: qcom: llcc: simplify with cleanup.h
  firmware: qcom: tzmem: simplify returning pointer without cleanup
  soc: qcom: socinfo: Add PM6350 PMIC
  arm64: dts: renesas: rz-smarc: Replace fixed regulator for USB VBUS
  ...
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torvalds committed Jul 16, 2024
2 parents 99298eb + 49e24c8 commit cc0f7c3
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113 changes: 113 additions & 0 deletions Documentation/ABI/testing/sysfs-bus-i2c-devices-turris-omnia-mcu
Original file line number Diff line number Diff line change
@@ -0,0 +1,113 @@
What: /sys/bus/i2c/devices/<mcu_device>/board_revision
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Contains board revision number.

Only available if board information is burned in the MCU (older
revisions have board information burned in the ATSHA204-A chip).

Format: %u.

What: /sys/bus/i2c/devices/<mcu_device>/first_mac_address
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Contains device first MAC address. Each Turris Omnia is
allocated 3 MAC addresses. The two additional addresses are
computed from the first one by incrementing it.

Only available if board information is burned in the MCU (older
revisions have board information burned in the ATSHA204-A chip).

Format: %pM.

What: /sys/bus/i2c/devices/<mcu_device>/front_button_mode
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RW) The front button on the Turris Omnia router can be
configured either to change the intensity of all the LEDs on the
front panel, or to send the press event to the CPU as an
interrupt.

This file switches between these two modes:
- "mcu" makes the button press event be handled by the MCU to
change the LEDs panel intensity.
- "cpu" makes the button press event be handled by the CPU.

Format: %s.

What: /sys/bus/i2c/devices/<mcu_device>/front_button_poweron
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RW) Newer versions of the microcontroller firmware of the
Turris Omnia router support powering off the router into true
low power mode. The router can be powered on by pressing the
front button.

This file configures whether front button power on is enabled.

This file is present only if the power off feature is supported
by the firmware.

Format: %i.

What: /sys/bus/i2c/devices/<mcu_device>/fw_features
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Newer versions of the microcontroller firmware report the
features they support. These can be read from this file. If the
MCU firmware is too old, this file reads 0x0.

Format: 0x%x.

What: /sys/bus/i2c/devices/<mcu_device>/fw_version_hash_application
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Contains the version hash (commit hash) of the application
part of the microcontroller firmware.

Format: %s.

What: /sys/bus/i2c/devices/<mcu_device>/fw_version_hash_bootloader
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Contains the version hash (commit hash) of the bootloader
part of the microcontroller firmware.

Format: %s.

What: /sys/bus/i2c/devices/<mcu_device>/mcu_type
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Contains the microcontroller type (STM32, GD32, MKL).

Format: %s.

What: /sys/bus/i2c/devices/<mcu_device>/reset_selector
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Contains the selected factory reset level, determined by
how long the rear reset button was held by the user during board
reset.

Format: %i.

What: /sys/bus/i2c/devices/<mcu_device>/serial_number
Date: September 2024
KernelVersion: 6.11
Contact: Marek Behún <[email protected]>
Description: (RO) Contains the 64-bit board serial number in hexadecimal
format.

Only available if board information is burned in the MCU (older
revisions have board information burned in the ATSHA204-A chip).

Format: %016X.
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ description: |
initialized early into boot process and provides services to Operating Systems
on multiple processors including ones running Linux.
See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
The TI-SCI node describes the Texas Instrument's System Controller entity node.
This parent node may optionally have additional children nodes which describe
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55 changes: 54 additions & 1 deletion Documentation/devicetree/bindings/cache/qcom,llcc.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ properties:
compatible:
enum:
- qcom,qdu1000-llcc
- qcom,sa8775p-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
Expand Down Expand Up @@ -79,6 +80,33 @@ allOf:
- const: llcc0_base
- const: llcc_broadcast_base

- if:
properties:
compatible:
contains:
enum:
- qcom,sa8775p-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC4 base register region
- description: LLCC5 base register region
- description: LLCC broadcast base register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc4_base
- const: llcc5_base
- const: llcc_broadcast_base

- if:
properties:
compatible:
Expand Down Expand Up @@ -141,8 +169,31 @@ allOf:
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
then:
properties:
reg:
items:
- description: LLCC0 base register region
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC broadcast base register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc_broadcast_base

- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
then:
properties:
reg:
Expand All @@ -151,14 +202,16 @@ allOf:
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- description: LLCC broadcast base register region
- description: LLCC broadcast OR register region
- description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
- const: llcc3_base
- const: llcc_broadcast_base
- const: llcc_broadcast_and_base

additionalProperties: false

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Original file line number Diff line number Diff line change
@@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive StarLink Cache Controller

maintainers:
- Joshua Yeong <[email protected]>

description:
StarFive's StarLink Cache Controller manages the L3 cache shared between
clusters of CPU cores. The cache driver enables RISC-V non-standard cache
management as an alternative to instructions in the RISC-V Zicbom extension.

allOf:
- $ref: /schemas/cache-controller.yaml#

# We need a select here so we don't match all nodes with 'cache'
select:
properties:
compatible:
contains:
enum:
- starfive,jh8100-starlink-cache

required:
- compatible

properties:
compatible:
items:
- const: starfive,jh8100-starlink-cache
- const: cache

reg:
maxItems: 1

unevaluatedProperties: false

required:
- compatible
- reg
- cache-block-size
- cache-level
- cache-sets
- cache-size
- cache-unified

examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
cache-controller@15000000 {
compatible = "starfive,jh8100-starlink-cache", "cache";
reg = <0x0 0x15000000 0x0 0x278>;
cache-block-size = <64>;
cache-level = <3>;
cache-sets = <8192>;
cache-size = <0x400000>;
cache-unified;
};
};
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ properties:

The second cell should contain the clock ID.

Please see http://processors.wiki.ti.com/index.php/TISCI for
Please see https://software-dl.ti.com/tisci/esd/latest/index.html for
protocol documentation for the values to be used for different devices.

additionalProperties: false
Expand Down
12 changes: 8 additions & 4 deletions Documentation/devicetree/bindings/firmware/arm,scmi.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -72,14 +72,17 @@ properties:
- const: tx
- const: tx_reply
- const: rx
- const: rx_reply
minItems: 2

mboxes:
description:
List of phandle and mailbox channel specifiers. It should contain
exactly one, two or three mailboxes; the first one or two for transmitting
messages ("tx") and another optional ("rx") for receiving notifications
and delayed responses, if supported by the platform.
exactly one, two, three or four mailboxes; the first one or two for
transmitting messages ("tx") and another optional ("rx") for receiving
notifications and delayed responses, if supported by the platform.
The optional ("rx_reply") is for notifications completion interrupt,
if supported by the platform.
The number of mailboxes needed for transmitting messages depends on the
type of channels exposed by the specific underlying mailbox controller;
one single channel descriptor is enough if such channel is bidirectional,
Expand All @@ -92,9 +95,10 @@ properties:
2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels
2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels
3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels
4 mbox / 2 shmem => SCMI TX and RX over 4 mailbox unidirectional channels
Any other combination of mboxes and shmem is invalid.
minItems: 1
maxItems: 3
maxItems: 4

shmem:
description:
Expand Down
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