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Merge tag 'pm-5.14-rc1-2' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/rafael/linux-pm Pull more power management updates from Rafael Wysocki: "These include cpufreq core simplifications and fixes, cpufreq driver updates, cpuidle driver update, a generic power domains (genpd) locking fix and a debug-related simplification of the PM core. Specifics: - Drop the ->stop_cpu() (not really useful) and ->resolve_freq() (unused) cpufreq driver callbacks and modify the users of the former accordingly (Viresh Kumar, Rafael Wysocki). - Add frequency invariance support to the ACPI CPPC cpufreq driver again along with the related fixes and cleanups (Viresh Kumar). - Update the Meditak, qcom and SCMI ARM cpufreq drivers (Fabien Parent, Seiya Wang, Sibi Sankar, Christophe JAILLET). - Rename black/white-lists in the DT cpufreq driver (Viresh Kumar). - Add generic performance domains support to the dvfs DT bindings (Sudeep Holla). - Refine locking in the generic power domains (genpd) support code to avoid lock dependency issues (Stephen Boyd). - Update the MSM and qcom ARM cpuidle drivers (Bartosz Dudziak). - Simplify the PM core debug code by using ktime_us_delta() to compute time interval lengths (Mark-PK Tsai)" * tag 'pm-5.14-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (21 commits) PM: domains: Shrink locking area of the gpd_list_lock PM: sleep: Use ktime_us_delta() in initcall_debug_report() cpufreq: CPPC: Add support for frequency invariance arch_topology: Avoid use-after-free for scale_freq_data cpufreq: CPPC: Pass structure instance by reference cpufreq: CPPC: Fix potential memleak in cppc_cpufreq_cpu_init cpufreq: Remove ->resolve_freq() cpufreq: Reuse cpufreq_driver_resolve_freq() in __cpufreq_driver_target() cpufreq: Remove the ->stop_cpu() driver callback cpufreq: powernv: Migrate to ->exit() callback instead of ->stop_cpu() cpufreq: CPPC: Migrate to ->exit() callback instead of ->stop_cpu() cpufreq: intel_pstate: Combine ->stop_cpu() and ->offline() cpuidle: qcom: Add SPM register data for MSM8226 dt-bindings: arm: msm: Add SAW2 for MSM8226 dt-bindings: cpufreq: update cpu type and clock name for MT8173 SoC clk: mediatek: remove deprecated CLK_INFRA_CA57SEL for MT8173 SoC cpufreq: dt: Rename black/white-lists cpufreq: scmi: Fix an error message cpufreq: mediatek: add support for mt8365 dt-bindings: dvfs: Add support for generic performance domains ...
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Documentation/devicetree/bindings/dvfs/performance-domain.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Generic performance domains | ||
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maintainers: | ||
- Sudeep Holla <[email protected]> | ||
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description: |+ | ||
This binding is intended for performance management of groups of devices or | ||
CPUs that run in the same performance domain. Performance domains must not | ||
be confused with power domains. A performance domain is defined by a set | ||
of devices that always have to run at the same performance level. For a given | ||
performance domain, there is a single point of control that affects all the | ||
devices in the domain, making it impossible to set the performance level of | ||
an individual device in the domain independently from other devices in | ||
that domain. For example, a set of CPUs that share a voltage domain, and | ||
have a common frequency control, is said to be in the same performance | ||
domain. | ||
This device tree binding can be used to bind performance domain consumer | ||
devices with their performance domains provided by performance domain | ||
providers. A performance domain provider can be represented by any node in | ||
the device tree and can provide one or more performance domains. A consumer | ||
node can refer to the provider by a phandle and a set of phandle arguments | ||
(so called performance domain specifiers) of length specified by the | ||
\#performance-domain-cells property in the performance domain provider node. | ||
select: true | ||
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properties: | ||
"#performance-domain-cells": | ||
description: | ||
Number of cells in a performance domain specifier. Typically 0 for nodes | ||
representing a single performance domain and 1 for nodes providing | ||
multiple performance domains (e.g. performance controllers), but can be | ||
any value as specified by device tree binding documentation of particular | ||
provider. | ||
enum: [ 0, 1 ] | ||
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performance-domains: | ||
$ref: '/schemas/types.yaml#/definitions/phandle-array' | ||
maxItems: 1 | ||
description: | ||
A phandle and performance domain specifier as defined by bindings of the | ||
performance controller/provider specified by phandle. | ||
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additionalProperties: true | ||
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examples: | ||
- | | ||
performance: performance-controller@12340000 { | ||
compatible = "qcom,cpufreq-hw"; | ||
reg = <0x12340000 0x1000>; | ||
#performance-domain-cells = <1>; | ||
}; | ||
// The node above defines a performance controller that is a performance | ||
// domain provider and expects one cell as its phandle argument. | ||
cpus { | ||
#address-cells = <2>; | ||
#size-cells = <0>; | ||
cpu@0 { | ||
device_type = "cpu"; | ||
compatible = "arm,cortex-a57"; | ||
reg = <0x0 0x0>; | ||
performance-domains = <&performance 1>; | ||
}; | ||
}; |
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