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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kerne…
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…l/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This a large collection of clk driver updates and a handful of new SoC
  clk driver support.

  We have the usual Qualcomm clk drivers, along with clk drivers for the
  Sophgo and T-Head vendors, all to support some new SoCs.

  Nothing in particular stands out to me in the updates. There's the
  interconnect clk driver which exposes clks as interconnects, crossing
  subsystems. There's a bunch of janitorial things that are improving
  drivers in general like kmemdup_array() or fixing error paths. But
  overall the updates look normal to fix the description data which is
  usually the stuff that's wrong and/or untested.

  Core:
   - Skip gate basic type KUnit tests on s390 due to lack of MMIO
     emulation

  New Drivers:
   - AP sub-system clock controller in the T-Head TH1520
   - Sophgo Sophon sg2042 clk driver
   - Qualcomm SM7150 camera, display and video clk drivers
   - Qualcomm QCM2290 GPU clk driver
   - Qualcomm QCS8386/QCS8084 NSS clk driver
   - Qualcomm SM8650 camera and video drivers

  Updates:
   - Add reset support to Airoha EN7581 clk driver
   - Add MODULE_DESCRIPTIONs to various clk drivers
   - Introduce helper logic to expose clock controllers as simple
     interconnect providers
   - Use the interconnect helper above on Qualcomm ipq9574
   - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on
     Qualcomm X1Elite
   - Improve error handling in Qualcomm kpss-xcc driver
   - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
   - Export more clocks for Rockchip rk3128 peripherals
   - Convert Rockchip clk drivers to use kmemdup_array()
   - Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
   - Make qcom_cc_really_probe() take a struct device to allow reuse in
     non-platform-drivers
   - Introduce prepare-only branch clock ops in the qcom clk driver to
     support clocks on buses that take locks
   - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
   - Support Qualcomm Huayra 2290 alpha PLL
   - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to
     match HS200 support
   - Add missing PCIe PIPE clocks on Qualcomm IPQ9574
   - Fix various configurations and properties in the Qualcomm SA8775P,
     X1E80100 and SM7280 drivers
   - Park Qualcomm SM8350 GPU RCGs on XO while disabled
   - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
   - exynos-clkout: Remove usage of of_device_id table as
     .of_match_table, because the driver is instantiated as MFD cell,
     not as standalone platform driver. Populated .of_match_table
     confused people few times to convert the code to
     device_get_match_data(), which broke the driver
   - Mark one Samsung UFS clock as critical, because having it off stops
     the system from shutdown
   - Use kmemdup_array() when applicable
   - Remove unused 'struct gates_data' from old sunxi driver library
   - Add GPADC clock and reset for Allwinner H616
   - Minor Amlogic S4 clock fixes
   - DT bindings Yaml conversion of the Amlogic AXG audio controller
   - Amlogic C3 clock controllers support
   - Amlogic clk flag added to skip init of already enabled PLLs and
     avoid relocking
   - Amlogic A1 DT bindings updates for system pll support
   - Add missing MODULE_DESCRIPTION where necessary
   - Remove obsolete clock DT binding header files
   - Add Battery Backup (VBATTB) and I2C clocks, resets, and power
     domains on Renesas RZ/G3S
   - Add audio clocks on Renesas R-Car V4M
   - Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
  clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
  dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
  clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
  clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
  clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
  clk: sunxi-ng r40: Constify struct regmap_config
  clk: en7523: fix rate divider for slic and spi clocks
  clk: lpc32xx: Constify struct regmap_config
  clk: xilinx: Constify struct regmap_config
  clk: en7523: Remove PCIe reset open drain configuration for EN7581
  clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
  clk: en7523: Add reset-controller support for EN7581 SoC
  dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
  dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
  clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
  dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
  dt-bindings: clock: sprd,sc9860-clk: convert to YAML
  dt-bindings: clock: qoriq-clock: convert to yaml format
  clk: qcom: Park shared RCGs upon registration
  clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
  ...
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torvalds committed Jul 19, 2024
2 parents f4f92db + 589eb11 commit a4f9285
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25 changes: 24 additions & 1 deletion Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -35,14 +35,18 @@ properties:

reg:
minItems: 2
maxItems: 3
maxItems: 4

"#clock-cells":
description:
The first cell indicates the clock number, see [1] for available
clocks.
const: 1

'#reset-cells':
description: ID of the controller reset line
const: 1

required:
- compatible
- reg
Expand All @@ -60,6 +64,8 @@ allOf:
- description: scu base address
- description: misc scu base address

'#reset-cells': false

- if:
properties:
compatible:
Expand All @@ -70,6 +76,7 @@ allOf:
items:
- description: scu base address
- description: misc scu base address
- description: reset base address
- description: pb scu base address

additionalProperties: false
Expand All @@ -83,3 +90,19 @@ examples:
<0x1fb00000 0x1000>;
#clock-cells = <1>;
};
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
scuclk: clock-controller@1fa20000 {
compatible = "airoha,en7581-scu";
reg = <0x0 0x1fa20000 0x0 0x400>,
<0x0 0x1fb00000 0x0 0x90>,
<0x0 0x1fb00830 0x0 0x8>,
<0x0 0x1fbe3400 0x0 0xfc>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,8 @@ properties:
- description: input fixed pll div7
- description: input hifi pll
- description: input oscillator (usually at 24MHz)
- description: input sys pll
minItems: 6 # sys_pll is optional

clock-names:
items:
Expand All @@ -39,6 +41,8 @@ properties:
- const: fclk_div7
- const: hifi_pll
- const: xtal
- const: sys_pll
minItems: 6 # sys_pll is optional

required:
- compatible
Expand All @@ -65,9 +69,10 @@ examples:
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_HIFI_PLL>,
<&xtal>;
<&xtal>,
<&clkc_pll CLKID_SYS_PLL>;
clock-names = "fclk_div2", "fclk_div3",
"fclk_div5", "fclk_div7",
"hifi_pll", "xtal";
"hifi_pll", "xtal", "sys_pll";
};
};
Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,15 @@ properties:
items:
- description: input fixpll_in
- description: input hifipll_in
- description: input syspll_in
minItems: 2 # syspll_in is optional

clock-names:
items:
- const: fixpll_in
- const: hifipll_in
- const: syspll_in
minItems: 2 # syspll_in is optional

required:
- compatible
Expand All @@ -53,7 +57,8 @@ examples:
reg = <0 0x7c80 0 0x18c>;
#clock-cells = <1>;
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
<&clkc_periphs CLKID_HIFIPLL_IN>;
clock-names = "fixpll_in", "hifipll_in";
<&clkc_periphs CLKID_HIFIPLL_IN>,
<&clkc_periphs CLKID_SYSPLL_IN>;
clock-names = "fixpll_in", "hifipll_in", "syspll_in";
};
};
59 changes: 0 additions & 59 deletions Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

This file was deleted.

201 changes: 201 additions & 0 deletions Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,201 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic AXG Audio Clock Controller

maintainers:
- Neil Armstrong <[email protected]>
- Jerome Brunet <[email protected]>

description:
The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.

properties:
compatible:
enum:
- amlogic,axg-audio-clkc
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc

'#clock-cells':
const: 1

'#reset-cells':
const: 1

reg:
maxItems: 1

clocks:
minItems: 1
items:
- description: main peripheral bus clock
- description: input plls to generate clock signals N0
- description: input plls to generate clock signals N1
- description: input plls to generate clock signals N2
- description: input plls to generate clock signals N3
- description: input plls to generate clock signals N4
- description: input plls to generate clock signals N5
- description: input plls to generate clock signals N6
- description: input plls to generate clock signals N7
- description: slave bit clock N0 provided by external components
- description: slave bit clock N1 provided by external components
- description: slave bit clock N2 provided by external components
- description: slave bit clock N3 provided by external components
- description: slave bit clock N4 provided by external components
- description: slave bit clock N5 provided by external components
- description: slave bit clock N6 provided by external components
- description: slave bit clock N7 provided by external components
- description: slave bit clock N8 provided by external components
- description: slave bit clock N9 provided by external components
- description: slave sample clock N0 provided by external components
- description: slave sample clock N1 provided by external components
- description: slave sample clock N2 provided by external components
- description: slave sample clock N3 provided by external components
- description: slave sample clock N4 provided by external components
- description: slave sample clock N5 provided by external components
- description: slave sample clock N6 provided by external components
- description: slave sample clock N7 provided by external components
- description: slave sample clock N8 provided by external components
- description: slave sample clock N9 provided by external components

clock-names:
minItems: 1
items:
- const: pclk
- const: mst_in0
- const: mst_in1
- const: mst_in2
- const: mst_in3
- const: mst_in4
- const: mst_in5
- const: mst_in6
- const: mst_in7
- const: slv_sclk0
- const: slv_sclk1
- const: slv_sclk2
- const: slv_sclk3
- const: slv_sclk4
- const: slv_sclk5
- const: slv_sclk6
- const: slv_sclk7
- const: slv_sclk8
- const: slv_sclk9
- const: slv_lrclk0
- const: slv_lrclk1
- const: slv_lrclk2
- const: slv_lrclk3
- const: slv_lrclk4
- const: slv_lrclk5
- const: slv_lrclk6
- const: slv_lrclk7
- const: slv_lrclk8
- const: slv_lrclk9

resets:
description: internal reset line

required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
- resets

allOf:
- if:
properties:
compatible:
contains:
enum:
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc
then:
required:
- '#reset-cells'
else:
properties:
'#reset-cells': false

additionalProperties: false

examples:
- |
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
apb {
#address-cells = <2>;
#size-cells = <2>;
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>,
<&slv_sclk0>,
<&slv_sclk1>,
<&slv_sclk2>,
<&slv_sclk3>,
<&slv_sclk4>,
<&slv_sclk5>,
<&slv_sclk6>,
<&slv_sclk7>,
<&slv_sclk8>,
<&slv_sclk9>,
<&slv_lrclk0>,
<&slv_lrclk1>,
<&slv_lrclk2>,
<&slv_lrclk3>,
<&slv_lrclk4>,
<&slv_lrclk5>,
<&slv_lrclk6>,
<&slv_lrclk7>,
<&slv_lrclk8>,
<&slv_lrclk9>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7",
"slv_sclk0",
"slv_sclk1",
"slv_sclk2",
"slv_sclk3",
"slv_sclk4",
"slv_sclk5",
"slv_sclk6",
"slv_sclk7",
"slv_sclk8",
"slv_sclk9",
"slv_lrclk0",
"slv_lrclk1",
"slv_lrclk2",
"slv_lrclk3",
"slv_lrclk4",
"slv_lrclk5",
"slv_lrclk6",
"slv_lrclk7",
"slv_lrclk8",
"slv_lrclk9";
resets = <&reset RESET_AUDIO>;
};
};
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