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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/soc/soc Pull ARM SoC fixes from Olof Johansson: "I had queued up a batch of fixes that got a bit close to the release for sending in before the merge window opened, so I'm including them in the merge window batch instead. Mostly smaller DT tweaks and fixes, the usual mix that we tend to have through the releases" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: dts: iwg20d-q7-common: Fix touch controller probe failure ARM: OMAP2+: Restore MPU power domain if cpu_cluster_pm_enter() fails ARM: dts: am33xx: modify AM33XX_IOPAD for #pinctrl-cells = 2 soc: actions: include header to fix missing prototype arm64: dts: ti: k3-j721e: Rename mux header and update macro names soc: qcom: pdr: Fixup array type of get_domain_list_resp message arm64: dts: qcom: pm660: Fix missing pound sign in interrupt-cells arm64: dts: qcom: kitakami: Temporarily disable SDHCI1 arm64: dts: sdm630: Temporarily disable SMMUs by default arm64: dts: sdm845: Fixup OPP table for all qup devices arm64: dts: allwinner: h5: remove Mali GPU PMU module ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulator soc: xilinx: Fix error code in zynqmp_pm_probe()
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
/* | ||
* This header provides constants for SERDES MUX for TI SoCs | ||
*/ | ||
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#ifndef _DT_BINDINGS_MUX_TI_SERDES | ||
#define _DT_BINDINGS_MUX_TI_SERDES | ||
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/* J721E */ | ||
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#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 | ||
#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 | ||
#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 | ||
#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 | ||
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#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 | ||
#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 | ||
#define J721E_SERDES0_LANE1_USB3_0 0x2 | ||
#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 | ||
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#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 | ||
#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 | ||
#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 | ||
#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 | ||
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#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 | ||
#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 | ||
#define J721E_SERDES1_LANE1_USB3_1 0x2 | ||
#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 | ||
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#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 | ||
#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 | ||
#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 | ||
#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 | ||
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#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 | ||
#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 | ||
#define J721E_SERDES2_LANE1_USB3_1 0x2 | ||
#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 | ||
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#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 | ||
#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 | ||
#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 | ||
#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 | ||
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#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 | ||
#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 | ||
#define J721E_SERDES3_LANE1_USB3_0 0x2 | ||
#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 | ||
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#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 | ||
#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 | ||
#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 | ||
#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 | ||
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#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 | ||
#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 | ||
#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 | ||
#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 | ||
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#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 | ||
#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 | ||
#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 | ||
#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 | ||
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#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 | ||
#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 | ||
#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 | ||
#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 | ||
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#endif /* _DT_BINDINGS_MUX_TI_SERDES */ |
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