forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 4
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge tag 'devicetree-for-5.1' of git://git.kernel.org/pub/scm/linux/…
…kernel/git/robh/linux Pull Devicetree updates from Rob Herring: - Fix a unittest failure on UML. Preparation for converting to kunit test framework. - Add annotations to dtx_diff output - Fix unittest reporting of expected error - Move DMA configuration for virtual devices into the driver that needs it (s5p-mfc) - Vendor prefixes for feiyang and techstar - Convert ARM GIC, GICv3, and L2x0 to DT schema - Add r8a7778/9 HSCIF serial bindings * tag 'devicetree-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: of: unittest: unflatten device tree on UML when testing dt-bindings: Add vendor prefix for feiyang dt-bindings: Add vendor prefix for techstar dt-bindings: display: add missing semicolon in example of: mark early_init_dt_alloc_reserved_memory_arch static of: add dtc annotations functionality to dtx_diff of: unittest: add caution to function header comment of: unittest: remove report of expected error dt-bindings: interrupt-controller: Convert ARM GICv3 to json-schema dt-bindings: interrupt-controller: Convert ARM GIC to json-schema dt-bindings: arm: l2x0: Convert L2 cache to json-schema media: s5p-mfc: Fix memdev DMA configuration dt-bindings: serial: sh-sci: Document r8a7778/9 HSCIF bindings
- Loading branch information
Showing
13 changed files
with
786 additions
and
476 deletions.
There are no files selected for viewing
This file was deleted.
Oops, something went wrong.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,248 @@ | ||
# SPDX-License-Identifier: GPL-2.0 | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/arm/l2c2x0.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
||
title: ARM L2 Cache Controller | ||
|
||
maintainers: | ||
- Rob Herring <[email protected]> | ||
|
||
description: |+ | ||
ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ | ||
PL220/PL310 and variants) based level 2 cache controller. All these various | ||
implementations of the L2 cache controller have compatible programming | ||
models (Note 1). Some of the properties that are just prefixed "cache-*" are | ||
taken from section 3.7.3 of the Devicetree Specification which can be found | ||
at: | ||
https://www.devicetree.org/specifications/ | ||
Note 1: The description in this document doesn't apply to integrated L2 | ||
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These | ||
integrated L2 controllers are assumed to be all preconfigured by | ||
early secure boot code. Thus no need to deal with their configuration | ||
in the kernel at all. | ||
allOf: | ||
- $ref: /schemas/cache-controller.yaml# | ||
|
||
properties: | ||
compatible: | ||
enum: | ||
- arm,pl310-cache | ||
- arm,l220-cache | ||
- arm,l210-cache | ||
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache" | ||
- bcm,bcm11351-a2-pl310-cache | ||
# For Broadcom bcm11351 chipset where an | ||
# offset needs to be added to the address before passing down to the L2 | ||
# cache controller | ||
- brcm,bcm11351-a2-pl310-cache | ||
# Marvell Controller designed to be | ||
# compatible with the ARM one, with system cache mode (meaning | ||
# maintenance operations on L1 are broadcasted to the L2 and L2 | ||
# performs the same operation). | ||
- marvell,aurora-system-cache | ||
# Marvell Controller designed to be | ||
# compatible with the ARM one with outer cache mode. | ||
- marvell,aurora-outer-cache | ||
# Marvell Tauros3 cache controller, compatible | ||
# with arm,pl310-cache controller. | ||
- marvell,tauros3-cache | ||
|
||
cache-level: | ||
const: 2 | ||
|
||
cache-unified: true | ||
cache-size: true | ||
cache-sets: true | ||
cache-block-size: true | ||
cache-line-size: true | ||
|
||
reg: | ||
maxItems: 1 | ||
|
||
arm,data-latency: | ||
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of | ||
read, write and setup latencies. Minimum valid values are 1. Controllers | ||
without setup latency control should use a value of 0. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32-array | ||
- minItems: 2 | ||
maxItems: 3 | ||
items: | ||
minimum: 0 | ||
maximum: 8 | ||
|
||
arm,tag-latency: | ||
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of | ||
read, write and setup latencies. Controllers without setup latency control | ||
should use 0. Controllers without separate read and write Tag RAM latency | ||
values should only use the first cell. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32-array | ||
- minItems: 1 | ||
maxItems: 3 | ||
items: | ||
minimum: 0 | ||
maximum: 8 | ||
|
||
arm,dirty-latency: | ||
description: Cycles of latency for Dirty RAMs. This is a single cell. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- minimum: 1 | ||
maximum: 8 | ||
|
||
arm,filter-ranges: | ||
description: <start length> Starting address and length of window to | ||
filter. Addresses in the filter window are directed to the M1 port. Other | ||
addresses will go to the M0 port. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32-array | ||
- items: | ||
minItems: 2 | ||
maxItems: 2 | ||
|
||
arm,io-coherent: | ||
description: indicates that the system is operating in an hardware | ||
I/O coherent mode. Valid only when the arm,pl310-cache compatible | ||
string is used. | ||
type: boolean | ||
|
||
interrupts: | ||
# Either a single combined interrupt or up to 9 individual interrupts | ||
minItems: 1 | ||
maxItems: 9 | ||
|
||
cache-id-part: | ||
description: cache id part number to be used if it is not present | ||
on hardware | ||
$ref: /schemas/types.yaml#/definitions/uint32 | ||
|
||
wt-override: | ||
description: If present then L2 is forced to Write through mode | ||
type: boolean | ||
|
||
arm,double-linefill: | ||
description: Override double linefill enable setting. Enable if | ||
non-zero, disable if zero. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
arm,double-linefill-incr: | ||
description: Override double linefill on INCR read. Enable | ||
if non-zero, disable if zero. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
arm,double-linefill-wrap: | ||
description: Override double linefill on WRAP read. Enable | ||
if non-zero, disable if zero. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
arm,prefetch-drop: | ||
description: Override prefetch drop enable setting. Enable if non-zero, | ||
disable if zero. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
arm,prefetch-offset: | ||
description: Override prefetch offset value. | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ] | ||
|
||
arm,shared-override: | ||
description: The default behavior of the L220 or PL310 cache | ||
controllers with respect to the shareable attribute is to transform "normal | ||
memory non-cacheable transactions" into "cacheable no allocate" (for reads) | ||
or "write through no write allocate" (for writes). | ||
On systems where this may cause DMA buffer corruption, this property must | ||
be specified to indicate that such transforms are precluded. | ||
type: boolean | ||
|
||
arm,parity-enable: | ||
description: enable parity checking on the L2 cache (L220 or PL310). | ||
type: boolean | ||
|
||
arm,parity-disable: | ||
description: disable parity checking on the L2 cache (L220 or PL310). | ||
type: boolean | ||
|
||
arm,outer-sync-disable: | ||
description: disable the outer sync operation on the L2 cache. | ||
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that | ||
will randomly hang unless outer sync operations are disabled. | ||
type: boolean | ||
|
||
prefetch-data: | ||
description: | | ||
Data prefetch. Value: <0> (forcibly disable), <1> | ||
(forcibly enable), property absent (retain settings set by firmware) | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
prefetch-instr: | ||
description: | | ||
Instruction prefetch. Value: <0> (forcibly disable), | ||
<1> (forcibly enable), property absent (retain settings set by | ||
firmware) | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
arm,dynamic-clock-gating: | ||
description: | | ||
L2 dynamic clock gating. Value: <0> (forcibly | ||
disable), <1> (forcibly enable), property absent (OS specific behavior, | ||
preferably retain firmware settings) | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
arm,standby-mode: | ||
description: L2 standby mode enable. Value <0> (forcibly disable), | ||
<1> (forcibly enable), property absent (OS specific behavior, | ||
preferably retain firmware settings) | ||
allOf: | ||
- $ref: /schemas/types.yaml#/definitions/uint32 | ||
- enum: [ 0, 1 ] | ||
|
||
arm,early-bresp-disable: | ||
description: Disable the CA9 optimization Early BRESP (PL310) | ||
type: boolean | ||
|
||
arm,full-line-zero-disable: | ||
description: Disable the CA9 optimization Full line of zero | ||
write (PL310) | ||
type: boolean | ||
|
||
required: | ||
- compatible | ||
- cache-unified | ||
- reg | ||
|
||
additionalProperties: false | ||
|
||
examples: | ||
- | | ||
cache-controller@fff12000 { | ||
compatible = "arm,pl310-cache"; | ||
reg = <0xfff12000 0x1000>; | ||
arm,data-latency = <1 1 1>; | ||
arm,tag-latency = <2 2 2>; | ||
arm,filter-ranges = <0x80000000 0x8000000>; | ||
cache-unified; | ||
cache-level = <2>; | ||
interrupts = <45>; | ||
}; | ||
... |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.