[AMDGPU][AsmParser] Eliminate validateExeczVcczOperands(). #102600
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Mention the names of unavailable registers in error messages to not make the diagnostics for execz/vccz less rich than it was. Clean up unnecessary name qualifications while there. Part of <llvm#62629>.
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-mc Author: Ivan Kosarev (kosarev) ChangesMention the names of unavailable registers in error messages to not make the diagnostics for execz/vccz less rich than it was. Clean up unnecessary name qualifications while there. Part of <#62629>. Patch is 63.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/102600.diff 18 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index bbd9d75aac0e91..ddd919b6900039 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1777,7 +1777,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const SMLoc &IDLoc);
bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
const unsigned CPol);
- bool validateExeczVcczOperands(const OperandVector &Operands);
bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
std::optional<StringRef> validateLdsDirect(const MCInst &Inst);
unsigned getConstantBusLimit(unsigned Opcode) const;
@@ -3039,7 +3038,8 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
if (Reg == AMDGPU::SGPR_NULL) {
Error(Loc, "'null' operand is not supported on this GPU");
} else {
- Error(Loc, "register not available on this GPU");
+ Error(Loc, Twine(AMDGPUInstPrinter::getRegisterName(Reg)) +
+ " register not available on this GPU");
}
return false;
}
@@ -5052,22 +5052,6 @@ bool AMDGPUAsmParser::validateTHAndScopeBits(const MCInst &Inst,
return true;
}
-bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
- if (!isGFX11Plus())
- return true;
- for (auto &Operand : Operands) {
- if (!Operand->isReg())
- continue;
- unsigned Reg = Operand->getReg();
- if (Reg == SRC_EXECZ || Reg == SRC_VCCZ) {
- Error(getRegLoc(Reg, Operands),
- "execz and vccz are not supported on this GPU");
- return false;
- }
- }
- return true;
-}
-
bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
const OperandVector &Operands) {
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
@@ -5203,9 +5187,6 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
if (!validateWaitCnt(Inst, Operands)) {
return false;
}
- if (!validateExeczVcczOperands(Operands)) {
- return false;
- }
if (!validateTFE(Inst, Operands)) {
return false;
}
@@ -6247,39 +6228,41 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
unsigned RegNo) {
-
- if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))
+ if (MRI.regsOverlap(TTMP12_TTMP13_TTMP14_TTMP15, RegNo))
return isGFX9Plus();
// GFX10+ has 2 more SGPRs 104 and 105.
- if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))
+ if (MRI.regsOverlap(SGPR104_SGPR105, RegNo))
return hasSGPR104_SGPR105();
switch (RegNo) {
- case AMDGPU::SRC_SHARED_BASE_LO:
- case AMDGPU::SRC_SHARED_BASE:
- case AMDGPU::SRC_SHARED_LIMIT_LO:
- case AMDGPU::SRC_SHARED_LIMIT:
- case AMDGPU::SRC_PRIVATE_BASE_LO:
- case AMDGPU::SRC_PRIVATE_BASE:
- case AMDGPU::SRC_PRIVATE_LIMIT_LO:
- case AMDGPU::SRC_PRIVATE_LIMIT:
+ case SRC_SHARED_BASE_LO:
+ case SRC_SHARED_BASE:
+ case SRC_SHARED_LIMIT_LO:
+ case SRC_SHARED_LIMIT:
+ case SRC_PRIVATE_BASE_LO:
+ case SRC_PRIVATE_BASE:
+ case SRC_PRIVATE_LIMIT_LO:
+ case SRC_PRIVATE_LIMIT:
return isGFX9Plus();
- case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
+ case SRC_POPS_EXITING_WAVE_ID:
return isGFX9Plus() && !isGFX11Plus();
- case AMDGPU::TBA:
- case AMDGPU::TBA_LO:
- case AMDGPU::TBA_HI:
- case AMDGPU::TMA:
- case AMDGPU::TMA_LO:
- case AMDGPU::TMA_HI:
+ case TBA:
+ case TBA_LO:
+ case TBA_HI:
+ case TMA:
+ case TMA_LO:
+ case TMA_HI:
return !isGFX9Plus();
- case AMDGPU::XNACK_MASK:
- case AMDGPU::XNACK_MASK_LO:
- case AMDGPU::XNACK_MASK_HI:
+ case XNACK_MASK:
+ case XNACK_MASK_LO:
+ case XNACK_MASK_HI:
return (isVI() || isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();
- case AMDGPU::SGPR_NULL:
+ case SGPR_NULL:
return isGFX10Plus();
+ case SRC_EXECZ:
+ case SRC_VCCZ:
+ return !isGFX11Plus();
default:
break;
}
@@ -6292,9 +6275,9 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
// On GFX10Plus flat scratch is not a valid register operand and can only be
// accessed with s_setreg/s_getreg.
switch (RegNo) {
- case AMDGPU::FLAT_SCR:
- case AMDGPU::FLAT_SCR_LO:
- case AMDGPU::FLAT_SCR_HI:
+ case FLAT_SCR:
+ case FLAT_SCR_LO:
+ case FLAT_SCR_HI:
return false;
default:
return true;
@@ -6303,7 +6286,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
// SI/CI have.
- if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))
+ if (MRI.regsOverlap(SGPR102_SGPR103, RegNo))
return hasSGPR102_SGPR103();
return true;
diff --git a/llvm/test/MC/AMDGPU/expressions.s b/llvm/test/MC/AMDGPU/expressions.s
index 5df128a122af07..f917347a3bd79a 100644
--- a/llvm/test/MC/AMDGPU/expressions.s
+++ b/llvm/test/MC/AMDGPU/expressions.s
@@ -337,4 +337,4 @@ v_sin_f32 v0, -s1000
xnack_mask_lo=1
v_sin_f32 v0, xnack_mask_lo
-// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: xnack_mask_lo register not available on this GPU
diff --git a/llvm/test/MC/AMDGPU/flat-scratch.s b/llvm/test/MC/AMDGPU/flat-scratch.s
index c4e8e6ef6a2cf7..745ac9e60067e6 100644
--- a/llvm/test/MC/AMDGPU/flat-scratch.s
+++ b/llvm/test/MC/AMDGPU/flat-scratch.s
@@ -5,32 +5,32 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
s_mov_b64 flat_scratch, -1
-// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU
// CI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x04,0xe8,0xbe]
// VI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x01,0xe6,0xbe]
s_mov_b32 flat_scratch_lo, -1
-// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_lo register not available on this GPU
// CI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x03,0xe8,0xbe]
// VI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x00,0xe6,0xbe]
s_mov_b32 flat_scratch_hi, -1
-// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_hi register not available on this GPU
// CI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x03,0xe9,0xbe]
// VI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x00,0xe7,0xbe]
s_mov_b64 flat_scratch_lo, -1
-// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_lo register not available on this GPU
// NOCI: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: invalid operand for instruction
s_mov_b64 flat_scratch_hi, -1
-// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch_hi register not available on this GPU
// NOCI: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: invalid operand for instruction
s_mov_b32 flat_scratch, -1
-// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSI: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU
// NOCI: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
// NOVI: :[[@LINE-3]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index d99da6e0cb8695..28060a7beec8f4 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -1124,12 +1124,12 @@ v_add_nc_i32 v256, v0, v1
// register not available on this GPU
s_and_b32 ttmp9, tma_hi, 0x0000ffff
-// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: tma_hi register not available on this GPU
// CHECK-NEXT:{{^}}s_and_b32 ttmp9, tma_hi, 0x0000ffff
// CHECK-NEXT:{{^}} ^
s_mov_b32 flat_scratch, -1
-// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU
// CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -1
// CHECK-NEXT:{{^}} ^
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_operands.s b/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
index d3efcf1987318c..bf08b7e287c20a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_operands.s
@@ -16,35 +16,35 @@ s_cbranch_execz 0x100
s_add_i32 s0, execz, s2
// GFX10: encoding: [0xfc,0x02,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
s_add_i32 s0, src_execz, s2
// GFX10: encoding: [0xfc,0x02,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
s_add_i32 s0, s1, execz
// GFX10: encoding: [0x01,0xfc,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
s_add_i32 s0, s1, src_execz
// GFX10: encoding: [0x01,0xfc,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
v_add_f64 v[0:1], execz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfc,0x04,0x02,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
v_add_f64 v[0:1], src_execz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfc,0x04,0x02,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
v_add_f64 v[0:1], v[1:2], execz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf9,0x01,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
v_add_f64 v[0:1], v[1:2], src_execz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf9,0x01,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_execz register not available on this GPU
//---------------------------------------------------------------------------//
// VCCZ
@@ -56,35 +56,35 @@ s_cbranch_vccz 0x100
s_add_i32 s0, vccz, s2
// GFX10: encoding: [0xfb,0x02,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
s_add_i32 s0, src_vccz, s2
// GFX10: encoding: [0xfb,0x02,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
s_add_i32 s0, s1, vccz
// GFX10: encoding: [0x01,0xfb,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
s_add_i32 s0, s1, src_vccz
// GFX10: encoding: [0x01,0xfb,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
v_add_f64 v[0:1], vccz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfb,0x04,0x02,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
v_add_f64 v[0:1], src_vccz, v[2:3]
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0xfb,0x04,0x02,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
v_add_f64 v[0:1], v[1:2], vccz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf7,0x01,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
v_add_f64 v[0:1], v[1:2], src_vccz
// GFX10: encoding: [0x00,0x00,0x64,0xd5,0x01,0xf7,0x01,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: execz and vccz are not supported on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_vccz register not available on this GPU
//---------------------------------------------------------------------------//
// LDS_DIRECT
@@ -112,32 +112,32 @@ v_mov_b32 v0, src_lds_direct
s_add_i32 s0, src_pops_exiting_wave_id, s1
// GFX10: encoding: [0xef,0x01,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
s_add_i32 s0, s1, src_pops_exiting_wave_id
// GFX10: encoding: [0x01,0xef,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
s_add_i32 s0, pops_exiting_wave_id, s1
// GFX10: encoding: [0xef,0x01,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
s_add_i32 s0, s1, pops_exiting_wave_id
// GFX10: encoding: [0x01,0xef,0x00,0x81]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
v_add_co_u32 v0, s0, pops_exiting_wave_id, v1
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0xef,0x02,0x02,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
v_add_co_u32 v0, s0, src_pops_exiting_wave_id, v1
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0xef,0x02,0x02,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
v_add_co_u32 v0, s0, v1, pops_exiting_wave_id
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0x01,0xdf,0x01,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
v_add_co_u32 v0, s0, v1, src_pops_exiting_wave_id
// GFX10: encoding: [0x00,0x00,0x0f,0xd7,0x01,0xdf,0x01,0x00]
-// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: register not available on this GPU
+// GFX11-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s
index 00575619c49f65..7b3bd5ece09884 100644
--- a/llvm/test/MC/AMDGPU/literals.s
+++ b/llvm/test/MC/AMDGPU/literals.s
@@ -650,89 +650,89 @@ v_ceil_f32_sdwa v5, |execz| dst_sel:DWORD src0_sel:DWORD
// named inline values: shared_base, shared_limit, private_base, etc
//---------------------------------------------------------------------------//
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU
// GFX9: buffer_atomic_add v0, off, s[0:3], src_shared_base offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xeb]
buffer_atomic_add v0, off, s[0:3], src_shared_base offset:4095
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU
// GFX9: s_add_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81]
s_add_i32 s0, src_shared_base, s0
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_limit register not available on this GPU
// GFX9: s_add_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81]
s_add_i32 s0, src_shared_limit, s0
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_base register not available on this GPU
// GFX9: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81]
s_add_i32 s0, src_private_base, s0
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_limit register not available on this GPU
// GFX9: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81]
s_add_i32 s0, src_private_limit, s0
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
// GFX9: s_add_i32 s0, src_pops_exiting_wave_id, s0 ; encoding: [0xef,0x00,0x00,0x81]
s_add_i32 s0, src_pops_exiting_wave_id, s0
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_base ; encoding: [0x00,0xeb,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_shared_base
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_shared_limit register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_shared_limit ; encoding: [0x00,0xec,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_shared_limit
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_base register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_private_base ; encoding: [0x00,0xed,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_private_base
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_private_limit register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_private_limit ; encoding: [0x00,0xee,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_private_limit
-// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: register not available on this GPU
+// NOSICIVI: :[[@LINE+2]]:{{[0-9]+}}: error: src_pops_exiting_wave_id register not available on this GPU
// GFX9: s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id ; encoding: [0x00,0xef,0x80,0x86]
s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id
// GFX9: v_add_u16_e32 v0, src_shared_base, v0 ; encoding: [0xeb,0x00,0x00,0x4c]
// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU
-// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: register not available on this GPU
+// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: src_shared_base register not available on this GPU
v_add_u16 v0, src_shared_base, v0
// GFX9: v_add_u16_sdwa v0, src_shared_base, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xeb,0x06,0x86,0x06]
// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU
-// NOVI: :[[@LINE+1]]:{{[0-9]+}}: error: register not available on this G...
[truncated]
|
rampitec
approved these changes
Aug 9, 2024
| @@ -3039,7 +3038,8 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, | |||
| if (Reg == AMDGPU::SGPR_NULL) { | |||
| Error(Loc, "'null' operand is not supported on this GPU"); | |||
| } else { | |||
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This else is probably not needed, Error shall act like a return.
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Actually it does not return, but can be used as return Error() instead.
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MCAsmParser::Error() seems to return true, so wouldn't work. (Confusingly, our AMDGPUAsmParser::Error() returns false, but from what I see that's not what we call here.)
| @@ -3039,7 +3038,8 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, | |||
| if (Reg == AMDGPU::SGPR_NULL) { | |||
| Error(Loc, "'null' operand is not supported on this GPU"); | |||
| } else { | |||
| Error(Loc, "register not available on this GPU"); | |||
| Error(Loc, Twine(AMDGPUInstPrinter::getRegisterName(Reg)) + | |||
| " register not available on this GPU"); | |||
| } | |||
| return false; | |||
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... and this line is dead.
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/72/builds/2156 Here is the relevant piece of the build log for the reference: |
bwendling
pushed a commit
to bwendling/llvm-project
that referenced
this pull request
Aug 15, 2024
Mention the names of unavailable registers in error messages to not make the diagnostics for execz/vccz less rich than it was. Clean up unnecessary name qualifications while there. Part of <llvm#62629>.
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Mention the names of unavailable registers in error messages to not make the diagnostics for execz/vccz less rich than it was.
Clean up unnecessary name qualifications while there.
Part of #62629.