Computer-Architecture-Lab-IUST

My solutions to IUST's Computer Architecture Laboratory, Spring 2022, Dr. Mohabbati.

Introduction

• Description: An Introduction PDF file providing an overview of the Computer Architecture Lab.
• Link to Introduction.pdf

Final Exam

• Description: The final exam in PDF format.
• Link to Final-Exam.pdf

Lab Sessions

Session1

• Description: Implementation of basic logic gates (or, and, xor), a half adder, and a full adder using two half adders.
• Code: Link to Session1 Code
• Report: Link to Session1 Report
• Note: Link to Session1 Lab Notes PDF

Session2

• Description: Implementation of MUX2TO1, MUX4TO1 using MUX2TO1, DECODER2TO4, ENCODER4TO2, and a 7-segment display.
• Code: Link to Session2 Code
• Report: Link to Session2 Report
• Note: Link to Session2 Lab Notes PDF

Session3

• Description: Implementation of D Flip Flop, JK Flip Flop, and T Flip Flop along with their test benches.
• Code: Link to Session3 Code
• Report: Link to Session3 Report
• Note: Link to Session3 Lab Notes PDF

Session4

• Description: Implementation of a Synchronous Decimal Count Up Counter Using T Flip Flop and a 4-bit binary down counter, along with their test benches.
• Code: Link to Session4 Code
• Report: Link to Session4 Report
• Note: Link to Session4 Lab Notes PDF

Session5

• Description: Implementation of 4-bit shift registers in different configurations (PIPO, PISO, SISO, SIPO) and their test benches.
• Code: Link to Session5 Code
• Note: Report: Link to Session5 Report
• Link to Session5 Lab Notes PDF

Session6

• Description: Implementation of Moore and Mealy state machines to accept the "0110" string and their test benches.
• Code: Link to Session6 Code
• Report: Link to Session6 Report
• Note: Link to Session6 Lab Notes PDF

Session7

• Description: Implementation of division in the ALU (Arithmetic Logic Unit) along with its test benches.
• Code: Link to Session7 Code
• Report: Link to Session7 Report
• Note: Link to Session7 Lab Notes PDF

Session8

• Description: Implementation of ROM (Read-Only Memory) and RAM (Random Access Memory) along with their test benches.
• Code: Link to Session8 Code
• Report: Link to Session8 Report
• Note: Link to Session8 Lab Notes PDF