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powerpc/85xx: Rework P1023RDS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1023-IP..." from compatibles for standard blocks * Removed incorrect power/pmc node, there are no etsec on P1023 Signed-off-by: Kumar Gala <[email protected]>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,224 @@ | ||
| /* | ||
| * P1023/P1017 Silicon/SoC Device Tree Source (post include) | ||
| * | ||
| * Copyright 2011 Freescale Semiconductor Inc. | ||
| * | ||
| * Redistribution and use in source and binary forms, with or without | ||
| * modification, are permitted provided that the following conditions are met: | ||
| * * Redistributions of source code must retain the above copyright | ||
| * notice, this list of conditions and the following disclaimer. | ||
| * * Redistributions in binary form must reproduce the above copyright | ||
| * notice, this list of conditions and the following disclaimer in the | ||
| * documentation and/or other materials provided with the distribution. | ||
| * * Neither the name of Freescale Semiconductor nor the | ||
| * names of its contributors may be used to endorse or promote products | ||
| * derived from this software without specific prior written permission. | ||
| * | ||
| * | ||
| * ALTERNATIVELY, this software may be distributed under the terms of the | ||
| * GNU General Public License ("GPL") as published by the Free Software | ||
| * Foundation, either version 2 of that License or (at your option) any | ||
| * later version. | ||
| * | ||
| * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY | ||
| * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||
| * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY | ||
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | ||
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | ||
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | ||
| * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | ||
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| */ | ||
|
|
||
| &lbc { | ||
| #address-cells = <2>; | ||
| #size-cells = <1>; | ||
| compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus"; | ||
| interrupts = <19 2 0 0>; | ||
| }; | ||
|
|
||
| /* controller at 0xa000 */ | ||
| &pci0 { | ||
| compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2"; | ||
| device_type = "pci"; | ||
| #size-cells = <2>; | ||
| #address-cells = <3>; | ||
| bus-range = <0x0 0xff>; | ||
| clock-frequency = <33333333>; | ||
| interrupts = <16 2 0 0>; | ||
| pcie@0 { | ||
| reg = <0 0 0 0 0>; | ||
| #interrupt-cells = <1>; | ||
| #size-cells = <2>; | ||
| #address-cells = <3>; | ||
| device_type = "pci"; | ||
| interrupts = <16 2 0 0>; | ||
| }; | ||
| }; | ||
|
|
||
| /* controller at 0x9000 */ | ||
| &pci1 { | ||
| compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2"; | ||
| device_type = "pci"; | ||
| #size-cells = <2>; | ||
| #address-cells = <3>; | ||
| bus-range = <0 0xff>; | ||
| clock-frequency = <33333333>; | ||
| interrupts = <16 2 0 0>; | ||
| pcie@0 { | ||
| reg = <0 0 0 0 0>; | ||
| #interrupt-cells = <1>; | ||
| #size-cells = <2>; | ||
| #address-cells = <3>; | ||
| device_type = "pci"; | ||
| interrupts = <16 2 0 0>; | ||
| }; | ||
| }; | ||
|
|
||
| /* controller at 0xb000 */ | ||
| &pci2 { | ||
| compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2"; | ||
| device_type = "pci"; | ||
| #size-cells = <2>; | ||
| #address-cells = <3>; | ||
| bus-range = <0x0 0xff>; | ||
| clock-frequency = <33333333>; | ||
| interrupts = <16 2 0 0>; | ||
| pcie@0 { | ||
| reg = <0 0 0 0 0>; | ||
| #interrupt-cells = <1>; | ||
| #size-cells = <2>; | ||
| #address-cells = <3>; | ||
| device_type = "pci"; | ||
| interrupts = <16 2 0 0>; | ||
| }; | ||
| }; | ||
|
|
||
| &soc { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| device_type = "soc"; | ||
| compatible = "fsl,p1023-immr", "simple-bus"; | ||
| bus-frequency = <0>; // Filled out by uboot. | ||
|
|
||
| ecm-law@0 { | ||
| compatible = "fsl,ecm-law"; | ||
| reg = <0x0 0x1000>; | ||
| fsl,num-laws = <12>; | ||
| }; | ||
|
|
||
| ecm@1000 { | ||
| compatible = "fsl,p1023-ecm", "fsl,ecm"; | ||
| reg = <0x1000 0x1000>; | ||
| interrupts = <16 2 0 0>; | ||
| }; | ||
|
|
||
| memory-controller@2000 { | ||
| compatible = "fsl,p1023-memory-controller"; | ||
| reg = <0x2000 0x1000>; | ||
| interrupts = <16 2 0 0>; | ||
| }; | ||
|
|
||
| /include/ "pq3-i2c-0.dtsi" | ||
| /include/ "pq3-i2c-1.dtsi" | ||
| /include/ "pq3-duart-0.dtsi" | ||
|
|
||
| /include/ "pq3-espi-0.dtsi" | ||
| spi@7000 { | ||
| fsl,espi-num-chipselects = <4>; | ||
| }; | ||
|
|
||
| /include/ "pq3-gpio-0.dtsi" | ||
|
|
||
| L2: l2-cache-controller@20000 { | ||
| compatible = "fsl,p1023-l2-cache-controller"; | ||
| reg = <0x20000 0x1000>; | ||
| cache-line-size = <32>; // 32 bytes | ||
| cache-size = <0x40000>; // L2,256K | ||
| interrupts = <16 2 0 0>; | ||
| }; | ||
|
|
||
| /include/ "pq3-dma-0.dtsi" | ||
| /include/ "pq3-usb2-dr-0.dtsi" | ||
|
|
||
| crypto: crypto@300000 { | ||
| compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| reg = <0x30000 0x10000>; | ||
| ranges = <0 0x30000 0x10000>; | ||
| interrupts = <58 2 0 0>; | ||
|
|
||
| sec_jr0: jr@1000 { | ||
| compatible = "fsl,sec-v4.2-job-ring", | ||
| "fsl,sec-v4.0-job-ring"; | ||
| reg = <0x1000 0x1000>; | ||
| interrupts = <45 2 0 0>; | ||
| }; | ||
|
|
||
| sec_jr1: jr@2000 { | ||
| compatible = "fsl,sec-v4.2-job-ring", | ||
| "fsl,sec-v4.0-job-ring"; | ||
| reg = <0x2000 0x1000>; | ||
| interrupts = <45 2 0 0>; | ||
| }; | ||
|
|
||
| sec_jr2: jr@3000 { | ||
| compatible = "fsl,sec-v4.2-job-ring", | ||
| "fsl,sec-v4.0-job-ring"; | ||
| reg = <0x3000 0x1000>; | ||
| interrupts = <57 2 0 0>; | ||
| }; | ||
|
|
||
| sec_jr3: jr@4000 { | ||
| compatible = "fsl,sec-v4.2-job-ring", | ||
| "fsl,sec-v4.0-job-ring"; | ||
| reg = <0x4000 0x1000>; | ||
| interrupts = <57 2 0 0>; | ||
| }; | ||
|
|
||
| rtic@6000 { | ||
| compatible = "fsl,sec-v4.2-rtic", | ||
| "fsl,sec-v4.0-rtic"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| reg = <0x6000 0x100>; | ||
| ranges = <0x0 0x6100 0xe00>; | ||
|
|
||
| rtic_a: rtic-a@0 { | ||
| compatible = "fsl,sec-v4.2-rtic-memory", | ||
| "fsl,sec-v4.0-rtic-memory"; | ||
| reg = <0x00 0x20 0x100 0x80>; | ||
| }; | ||
|
|
||
| rtic_b: rtic-b@20 { | ||
| compatible = "fsl,sec-v4.2-rtic-memory", | ||
| "fsl,sec-v4.0-rtic-memory"; | ||
| reg = <0x20 0x20 0x200 0x80>; | ||
| }; | ||
|
|
||
| rtic_c: rtic-c@40 { | ||
| compatible = "fsl,sec-v4.2-rtic-memory", | ||
| "fsl,sec-v4.0-rtic-memory"; | ||
| reg = <0x40 0x20 0x300 0x80>; | ||
| }; | ||
|
|
||
| rtic_d: rtic-d@60 { | ||
| compatible = "fsl,sec-v4.2-rtic-memory", | ||
| "fsl,sec-v4.0-rtic-memory"; | ||
| reg = <0x60 0x20 0x500 0x80>; | ||
| }; | ||
| }; | ||
| }; | ||
|
|
||
| /include/ "pq3-mpic.dtsi" | ||
| /include/ "pq3-mpic-timer-B.dtsi" | ||
|
|
||
| global-utilities@e0000 { | ||
| compatible = "fsl,p1023-guts"; | ||
| reg = <0xe0000 0x1000>; | ||
| fsl,has-rstcr; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,76 @@ | ||
| /* | ||
| * P1023/P1017 Silicon/SoC Device Tree Source (pre include) | ||
| * | ||
| * Copyright 2011 Freescale Semiconductor Inc. | ||
| * | ||
| * Redistribution and use in source and binary forms, with or without | ||
| * modification, are permitted provided that the following conditions are met: | ||
| * * Redistributions of source code must retain the above copyright | ||
| * notice, this list of conditions and the following disclaimer. | ||
| * * Redistributions in binary form must reproduce the above copyright | ||
| * notice, this list of conditions and the following disclaimer in the | ||
| * documentation and/or other materials provided with the distribution. | ||
| * * Neither the name of Freescale Semiconductor nor the | ||
| * names of its contributors may be used to endorse or promote products | ||
| * derived from this software without specific prior written permission. | ||
| * | ||
| * | ||
| * ALTERNATIVELY, this software may be distributed under the terms of the | ||
| * GNU General Public License ("GPL") as published by the Free Software | ||
| * Foundation, either version 2 of that License or (at your option) any | ||
| * later version. | ||
| * | ||
| * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY | ||
| * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||
| * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY | ||
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | ||
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | ||
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | ||
| * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | ||
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| */ | ||
|
|
||
| /dts-v1/; | ||
| / { | ||
| compatible = "fsl,P1023"; | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| interrupt-parent = <&mpic>; | ||
|
|
||
| aliases { | ||
| serial0 = &serial0; | ||
| serial1 = &serial1; | ||
| pci0 = &pci0; | ||
| pci1 = &pci1; | ||
| pci2 = &pci2; | ||
|
|
||
| crypto = &crypto; | ||
| sec_jr0 = &sec_jr0; | ||
| sec_jr1 = &sec_jr1; | ||
| sec_jr2 = &sec_jr2; | ||
| sec_jr3 = &sec_jr3; | ||
| rtic_a = &rtic_a; | ||
| rtic_b = &rtic_b; | ||
| rtic_c = &rtic_c; | ||
| rtic_d = &rtic_d; | ||
| }; | ||
|
|
||
| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
|
||
| PowerPC,P1023@0 { | ||
| device_type = "cpu"; | ||
| reg = <0x0>; | ||
| next-level-cache = <&L2>; | ||
| }; | ||
|
|
||
| PowerPC,P1023@1 { | ||
| device_type = "cpu"; | ||
| reg = <0x1>; | ||
| next-level-cache = <&L2>; | ||
| }; | ||
| }; | ||
| }; |
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