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ARM: at91/gpio: drop PIN_BASE
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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@plagnioj @arndb
plagnioj authored and arndb committed Nov 29, 2011
1 parent 3285e0e commit d0fbda9
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Showing 2 changed files with 195 additions and 195 deletions.
54 changes: 28 additions & 26 deletions arch/arm/mach-at91/gpio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -59,18 +59,17 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
}

static struct at91_gpio_chip gpio_chip[] = {
AT91_GPIO_CHIP("pioA", 0x00 + PIN_BASE, 32),
AT91_GPIO_CHIP("pioB", 0x20 + PIN_BASE, 32),
AT91_GPIO_CHIP("pioC", 0x40 + PIN_BASE, 32),
AT91_GPIO_CHIP("pioD", 0x60 + PIN_BASE, 32),
AT91_GPIO_CHIP("pioE", 0x80 + PIN_BASE, 32),
AT91_GPIO_CHIP("pioA", 0x00, 32),
AT91_GPIO_CHIP("pioB", 0x20, 32),
AT91_GPIO_CHIP("pioC", 0x40, 32),
AT91_GPIO_CHIP("pioD", 0x60, 32),
AT91_GPIO_CHIP("pioE", 0x80, 32),
};

static int gpio_banks;

static inline void __iomem *pin_to_controller(unsigned pin)
{
pin -= PIN_BASE;
pin /= 32;
if (likely(pin < gpio_banks))
return gpio_chip[pin].regbase;
Expand All @@ -80,7 +79,6 @@ static inline void __iomem *pin_to_controller(unsigned pin)

static inline unsigned pin_to_mask(unsigned pin)
{
pin -= PIN_BASE;
return 1 << (pin % 32);
}

Expand Down Expand Up @@ -275,8 +273,9 @@ static u32 backups[MAX_GPIO_BANKS];

static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
{
unsigned mask = pin_to_mask(d->irq);
unsigned bank = (d->irq - PIN_BASE) / 32;
unsigned pin = irq_to_gpio(d->irq);
unsigned mask = pin_to_mask(pin);
unsigned bank = pin / 32;

if (unlikely(bank >= MAX_GPIO_BANKS))
return -EINVAL;
Expand Down Expand Up @@ -345,17 +344,19 @@ void at91_gpio_resume(void)

static void gpio_irq_mask(struct irq_data *d)
{
void __iomem *pio = pin_to_controller(d->irq);
unsigned mask = pin_to_mask(d->irq);
unsigned pin = irq_to_gpio(d->irq);
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);

if (pio)
__raw_writel(mask, pio + PIO_IDR);
}

static void gpio_irq_unmask(struct irq_data *d)
{
void __iomem *pio = pin_to_controller(d->irq);
unsigned mask = pin_to_mask(d->irq);
unsigned pin = irq_to_gpio(d->irq);
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);

if (pio)
__raw_writel(mask, pio + PIO_IER);
Expand Down Expand Up @@ -383,7 +384,7 @@ static struct irq_chip gpio_irqchip = {

static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
unsigned pin;
unsigned irq_pin;
struct irq_data *idata = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(idata);
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
Expand All @@ -406,12 +407,12 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
continue;
}

pin = at91_gpio->chip.base;
irq_pin = gpio_to_irq(at91_gpio->chip.base);

while (isr) {
if (isr & 1)
generic_handle_irq(pin);
pin++;
generic_handle_irq(irq_pin);
irq_pin++;
isr >>= 1;
}
}
Expand Down Expand Up @@ -439,7 +440,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
seq_printf(s, "%i:\t", j);

for (bank = 0; bank < gpio_banks; bank++) {
unsigned pin = PIN_BASE + (32 * bank) + j;
unsigned pin = (32 * bank) + j;
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);

Expand Down Expand Up @@ -492,27 +493,28 @@ static struct lock_class_key gpio_lock_class;
*/
void __init at91_gpio_irq_setup(void)
{
unsigned pioc, pin;
unsigned pioc, irq = gpio_to_irq(0);
struct at91_gpio_chip *this, *prev;

for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
for (pioc = 0, this = gpio_chip, prev = NULL;
pioc++ < gpio_banks;
prev = this, this++) {
unsigned id = this->id;
unsigned i;

__raw_writel(~0, this->regbase + PIO_IDR);

for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
irq_set_lockdep_class(pin, &gpio_lock_class);
for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32;
i++, irq++) {
irq_set_lockdep_class(irq, &gpio_lock_class);

/*
* Can use the "simple" and not "edge" handler since it's
* shorter, and the AIC handles interrupts sanely.
*/
irq_set_chip_and_handler(pin, &gpio_irqchip,
irq_set_chip_and_handler(irq, &gpio_irqchip,
handle_simple_irq);
set_irq_flags(pin, IRQF_VALID);
set_irq_flags(irq, IRQF_VALID);
}

/* The toplevel handler handles one bank of GPIOs, except
Expand All @@ -525,7 +527,7 @@ void __init at91_gpio_irq_setup(void)
irq_set_chip_data(id, this);
irq_set_chained_handler(id, gpio_irq_handler);
}
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
pr_info("AT91: %d gpio irqs in %d banks\n", irq, gpio_banks);
}

/* gpiolib support */
Expand Down Expand Up @@ -614,7 +616,7 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
at91_gpio = &gpio_chip[i];

at91_gpio->id = data[i].id;
at91_gpio->chip.base = PIN_BASE + i * 32;
at91_gpio->chip.base = i * 32;

at91_gpio->regbase = ioremap(data[i].regbase, 512);
if (!at91_gpio->regbase) {
Expand Down
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