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Merge branch 'marco-timer-cleanup-rebase' of git://gitorious.org/sirf…
…prima2-kernel/sirfprima2-kernel into next/soc From Barry Song, this adds support for a new SoC from CSR; marco. It's SMP, uses GIC instead of VIC and in general needs a bit of rework of the platform code for setup, which this branch contains. * 'marco-timer-cleanup-rebase' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel: ARM: PRIMA2: provide two DEBUG_LL ports for prima2 and marco ARM: PRIMA2: add new SiRFmarco SMP SoC infrastructures ARM: PRIMA2: irq: make prima2 irq can work even we enable GIC for Marco ARM: PRIMA2: rtciobg: it is also compatible with marco ARM: PRIMA2: rstc: enable the support for Marco ARM: PRIMA2: mv timer to timer-prima2 as we will add timer-marco ARM: PRIMA2: initialize l2x0 according to mach from DT ARM: PRIMA2: enable AUTO_ZRELADDR for SIRF in Kconfig ARM: PRIMA2: add CSR SiRFmarco device tree .dts Signed-off-by: Olof Johansson <[email protected]>
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prima2 "cb" evaluation board | ||
CSR SiRFprimaII and SiRFmarco device tree bindings. | ||
======================================== | ||
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Required root node properties: | ||
- compatible = "sirf,prima2-cb", "sirf,prima2"; | ||
- compatible: | ||
- "sirf,prima2-cb" : prima2 "cb" evaluation board | ||
- "sirf,marco-cb" : marco "cb" evaluation board | ||
- "sirf,prima2" : prima2 device based board | ||
- "sirf,marco" : marco device based board |
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/* | ||
* DTS file for CSR SiRFmarco Evaluation Board | ||
* | ||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
* | ||
* Licensed under GPLv2 or later. | ||
*/ | ||
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/dts-v1/; | ||
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/include/ "marco.dtsi" | ||
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/ { | ||
model = "CSR SiRFmarco Evaluation Board"; | ||
compatible = "sirf,marco-cb", "sirf,marco"; | ||
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memory { | ||
reg = <0x40000000 0x60000000>; | ||
}; | ||
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axi { | ||
peri-iobg { | ||
uart1: uart@cc060000 { | ||
status = "okay"; | ||
}; | ||
uart2: uart@cc070000 { | ||
status = "okay"; | ||
}; | ||
i2c0: i2c@cc0e0000 { | ||
status = "okay"; | ||
fpga-cpld@4d { | ||
compatible = "sirf,fpga-cpld"; | ||
reg = <0x4d>; | ||
}; | ||
}; | ||
spi1: spi@cc170000 { | ||
status = "okay"; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&spi1_pins_a>; | ||
spi@0 { | ||
compatible = "spidev"; | ||
reg = <0>; | ||
spi-max-frequency = <1000000>; | ||
}; | ||
}; | ||
pci-iobg { | ||
sd0: sdhci@cd000000 { | ||
bus-width = <8>; | ||
status = "okay"; | ||
}; | ||
}; | ||
}; | ||
}; | ||
}; |
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