The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering

[MSST '24] Prophet: Optimizing LSM-Based Key-Value Store on ZNS SSDs with File Lifetime Prediction and Compaction Compensation.

Tiered memory management

A collection of awesome researchers and papers about disaggregated memory.

This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine grained scheduling, map back to compiler, cross platform live migr…

Artifacts of EuroSys'24 paper "Exploring Performance and Cost Optimization with ASIC-Based CXL Memory"

linux内核学习资料：200+经典内核文章，100+内核论文，50+内核项目，500+内核面试题，80+内核视频

A tutorial of building an LSM-Tree storage engine in a week!

CXL Memory Resource Kit top-level repository

Disaggregated memory tutorial.

This is the user space repo for famfs, the fabric-attached memory file system

x86汇编 从实模式到保护模式，mac版本

A "device memory" enabling project encompassing tools and libraries for CXL, NVDIMMs, DAX, memory tiering and other platform memory device topics.

Heterogeneous Memory Software Development Kit

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

This is the respository that holds the artifacts of MICRO'23 -- Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Devices

All documents and materials for LeetCode including basement C++ Grammar（真从零开始LeetCode，含C++、算法、数据结构解析）

Xilinx Embedded Software (embeddedsw) Development

HDLBits website practices & solutions

CXL Fabric Manager (FM) architecture documents

A place to store the CXL simulator

Linux kernel source tree of developing SMDK kernel for CXL Memory

深度学习经典、新论文逐段精读

Pond: CXL-Based Memory Pooling Systems for Cloud Platforms (ASPLOS'23)

A list of learning materials to understand databases internals

Linux kernel source tree

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logi…