Skip to content

Commit

Permalink
mxs: prefix register structs with 'mxs' prefix
Browse files Browse the repository at this point in the history 
Signed-off-by: Otavio Salvador <[email protected]>
  • Loading branch information
@otavio @albert-aribaud-u-boot
otavio authored and albert-aribaud-u-boot committed Sep 1, 2012
1 parent ddcf13b commit 9c47114
Show file tree
Hide file tree
Showing 32 changed files with 188 additions and 189 deletions.
36 changes: 18 additions & 18 deletions arch/arm/cpu/arm926ejs/mxs/clock.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@

static uint32_t mx28_get_pclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
Expand Down Expand Up @@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void)

static uint32_t mx28_get_hclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

uint32_t div;
uint32_t clkctrl;
Expand All @@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void)

static uint32_t mx28_get_emiclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
Expand All @@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void)

static uint32_t mx28_get_gpmiclk(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
Expand All @@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void)
*/
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
int io_reg;

Expand Down Expand Up @@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
*/
static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint8_t ret;
int io_reg;

Expand All @@ -199,8 +199,8 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
*/
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;

if (ssp > MXC_SSPCLK3)
Expand Down Expand Up @@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
*/
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkreg;
uint32_t clk, tmp;

Expand Down Expand Up @@ -273,12 +273,12 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
*/
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mx28_ssp_regs *ssp_regs;
struct mxs_ssp_regs *ssp_regs;
const uint32_t sspclk = mx28_get_sspclk(bus);
uint32_t reg;
uint32_t divide, rate, tgtclk;

ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));

/*
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
Expand Down
28 changes: 14 additions & 14 deletions arch/arm/cpu/arm926ejs/mxs/mx28.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,10 +51,10 @@ void reset_cpu(ulong ignored) __attribute__((noreturn));

void reset_cpu(ulong ignored)
{
struct mx28_rtc_regs *rtc_regs =
(struct mx28_rtc_regs *)MXS_RTC_BASE;
struct mx28_lcdif_regs *lcdif_regs =
(struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
struct mxs_lcdif_regs *lcdif_regs =
(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;

/*
* Shut down the LCD controller as it interferes with BootROM boot mode
Expand Down Expand Up @@ -155,8 +155,8 @@ int arch_misc_init(void)

int arch_cpu_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
extern uint32_t _start;

mx28_fixup_vt((uint32_t)&_start);
Expand Down Expand Up @@ -190,8 +190,8 @@ int arch_cpu_init(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
static const char *get_cpu_type(void)
{
struct mx28_digctl_regs *digctl_regs =
(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;

switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
case HW_DIGCTL_CHIPID_MX28:
Expand All @@ -203,8 +203,8 @@ static const char *get_cpu_type(void)

static const char *get_cpu_rev(void)
{
struct mx28_digctl_regs *digctl_regs =
(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;

switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
Expand Down Expand Up @@ -249,8 +249,8 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
#ifdef CONFIG_CMD_NET
int cpu_eth_init(bd_t *bis)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

/* Turn on ENET clocks */
clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
Expand Down Expand Up @@ -291,8 +291,8 @@ void mx28_adjust_mac(int dev_id, unsigned char *mac)
#define MXS_OCOTP_MAX_TIMEOUT 1000000
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
struct mx28_ocotp_regs *ocotp_regs =
(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
struct mxs_ocotp_regs *ocotp_regs =
(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
uint32_t data;

memset(mac, 0, 6);
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@

void mx28_lradc_init(void)
{
struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;

writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
Expand All @@ -51,7 +51,7 @@ void mx28_lradc_init(void)

void mx28_lradc_enable_batt_measurement(void)
{
struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;

/* Check if the channel is present at all. */
if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
Expand Down
24 changes: 12 additions & 12 deletions arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,8 @@ void init_mx28_200mhz_ddr2(void)

void mx28_mem_init_clock(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
Expand Down Expand Up @@ -131,8 +131,8 @@ void mx28_mem_init_clock(void)

void mx28_mem_setup_cpu_and_hbus(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
* and ungate CPU clock */
Expand Down Expand Up @@ -163,8 +163,8 @@ void mx28_mem_setup_cpu_and_hbus(void)

void mx28_mem_setup_vdda(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;

writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
Expand All @@ -174,8 +174,8 @@ void mx28_mem_setup_vdda(void)

void mx28_mem_setup_vddd(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;

writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
Expand Down Expand Up @@ -204,10 +204,10 @@ uint32_t mx28_mem_get_size(void)

void mx28_mem_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mx28_pinctrl_regs *pinctrl_regs =
(struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;

/* Set DDR2 mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
Expand Down
Loading

0 comments on commit 9c47114

Please sign in to comment.