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tinygrad Public
Forked from tinygrad/tinygradYou like pytorch? You like micrograd? You love tinygrad! ❤️
Python MIT License UpdatedMay 29, 2023 -
proteus Public
Forked from proteus-core/proteusThe SpinalHDL design of the Proteus core, an extensible RISC-V core.
Scala MIT License UpdatedMay 22, 2023 -
shuttle Public
Forked from ucb-bar/shuttleA Rocket-based RISC-V superscalar in-order core
Scala UpdatedMay 22, 2023 -
riscv_vhdl Public
Forked from sergeykhbr/riscv_vhdlPortable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Verilog Apache License 2.0 UpdatedMay 16, 2023 -
nngen Public
Forked from NNgen/nngenNNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Python Apache License 2.0 UpdatedMay 15, 2023 -
verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedMay 2, 2023 -
amaranth Public
Forked from amaranth-lang/amaranthA modern hardware definition language and toolchain based on Python
Python BSD 2-Clause "Simplified" License UpdatedApr 16, 2023 -
ara Public
Forked from pulp-platform/araThe PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
C Other UpdatedApr 2, 2023 -
ntnu-firesim Public
Forked from EECS-NTNU/firesimFireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
Scala Other UpdatedMar 21, 2023 -
riscv-vector-tests Public
Forked from chipsalliance/riscv-vector-testsThe missing test suite for RISC-V V extension.
Go MIT License UpdatedMar 17, 2023 -
verilog-pcie Public
Forked from alexforencich/verilog-pcieVerilog PCI express components
Verilog MIT License UpdatedFeb 18, 2023 -
verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedFeb 13, 2023 -
vroom Public
Forked from MoonbaseOtago/vroomVRoom! RISC-V CPU
Verilog GNU General Public License v3.0 UpdatedFeb 10, 2023 -
esp Public
Forked from sld-columbia/espEmbedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
C Other UpdatedFeb 3, 2023 -
XiangShan Public
Forked from OpenXiangShan/XiangShanOpen-source high-performance RISC-V processor
Scala Other UpdatedJan 3, 2023 -
riscv-ocelot Public
Forked from tenstorrent/riscv-ocelotOcelot: The Berkeley Out-of-Order Machine With V-EXT support
Verilog BSD 3-Clause "New" or "Revised" License UpdatedDec 13, 2022 -
vicuna Public
Forked from vproc/vicunaRISC-V Zve32x Vector Coprocessor
Assembly Other UpdatedDec 1, 2022 -
chipyard Public
Forked from ucb-bar/chipyardAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
C BSD 3-Clause "New" or "Revised" License UpdatedOct 25, 2022 -
rocket-chip-vcu128 Public
Forked from jiegec/rocket-chip-vcu128Run Rocket Chip on VCU128
Tcl MIT License UpdatedSep 30, 2022 -
CFU-Playground Public
Forked from google/CFU-PlaygroundWant a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online workshop: https://google.githu…
Verilog Apache License 2.0 UpdatedAug 26, 2022 -
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